Freezing Spice
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Awesome Hdl | 830 | 3 months ago | 1 | |||||||
| Hardware Description Languages | ||||||||||
| Edalize | 573 |  | 2 | 3 | 3 months ago | 24 | December 08, 2023 | 91 | bsd-2-clause | Python |
| An abstraction library for interfacing EDA tools | ||||||||||
| Pipelinec | 519 | 3 months ago | 82 | gpl-3.0 | Python | |||||
| A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature. | ||||||||||
| Poc | 324 | 4 years ago | 31 | other | VHDL | |||||
| IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany | ||||||||||
| Ghdl Yosys Plugin | 270 | 6 months ago | 28 | gpl-3.0 | VHDL | |||||
| VHDL synthesis (based on ghdl) | ||||||||||
| Yodl | 96 | 7 years ago | 2 | gpl-3.0 | C++ | |||||
| A VHDL frontend for Yosys | ||||||||||
| Freezing Spice | 88 | 5 years ago | 2 | bsd-3-clause | VHDL | |||||
| A pipelined RISCV implementation in VHDL | ||||||||||
| Reonv | 61 | 2 years ago | 6 | gpl-3.0 | VHDL | |||||
| ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 architecture, now changed to RISC-V ISA. | ||||||||||
| Json For Vhdl | 61 | 2 years ago | 7 | other | VHDL | |||||
| A JSON library implemented in VHDL. | ||||||||||
| Psl_with_ghdl | 54 | a year ago | 1 | lgpl-3.0 | VHDL | |||||
| Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys) | ||||||||||
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