Snes_mister
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Snes_mister | 173 | 4 months ago | 54 | gpl-3.0 | VHDL | |||||
| SNES for MiSTer | ||||||||||
| Rfsoc_qpsk | 62 | a year ago | bsd-3-clause | VHDL | ||||||
| PYNQ example of using the RFSoC as a QPSK transceiver. | ||||||||||
| Intfftk | 56 | a year ago | gpl-3.0 | VHDL | ||||||
| Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0. | ||||||||||
| Fpga Fft | 42 | 3 years ago | 1 | other | VHDL | |||||
| A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm | ||||||||||
| Fp23fftk | 31 | 2 years ago | gpl-3.0 | VHDL | ||||||
| Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL). | ||||||||||
| Hwthls | 20 | a year ago | mit | Python | ||||||
| LLVM based HLS library for HWToolkit (hardware devel. toolkit) | ||||||||||
| Math | 15 | 4 years ago | n,ull | gpl-3.0 | MATLAB | |||||
| Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.) | ||||||||||
| Dsp Cores | 11 | a year ago | 5 | lgpl-3.0 | VHDL | |||||
| Repository containing the DSP gateware cores | ||||||||||
| Em070_new Fpga Family For Cnn Architectures High Speed Soft Neuron Design | 10 | 6 years ago | VHDL | |||||||
| Who doesn’t dream of a new FPGA family that can provide embedded hard neurons in its silicon architecture fabric instead of the conventional DSP and multiplier blocks? The optimized hard neuron design will allow all the software and hardware designers to create or test different deep learning network architectures, especially the convolutional neural networks (CNN), more easily and faster in comparing to any previous FPGA family in the market nowadays. The revolutionary idea about this project is to open the gate of creativity for a precise-tailored new generation of FPGA families that can solve the problems of wasting logic resources and/or unneeded buses width as in the conventional DSP blocks nowadays. The project focusing on the anchor point of the any deep learning architecture, which is to design an optimized high-speed neuron block which should replace the conventional DSP blocks to avoid the drawbacks that designers face while trying to fit the CNN architecture design to it. The design of the proposed neuron also takes the parallelism operation concept as it’s primary keystone, beside the minimization of logic elements usage to construct the proposed neuron cell. The targeted neuron design resource usage is not to exceeds 500 ALM and the expected maximum operating frequency of 834.03 MHz for each neuron. In this project, ultra-fast, adaptive, and parallel modules are designed as soft blocks using VHDL code such as parallel Multipliers-Accumulators (MACs), RELU activation function that will contribute to open a new horizon for all the FPGA designers to build their own Convolutional Neural Networks (CNN). We couldn’t stop imagining INTEL ALTERA to lead the market by converting the proposed designed CNN block and to be a part of their new FPGA architecture fabrics in a separated new Logic Family so soon. The users of such proposed CNN blocks will be amazed from the high-speed operation per seconds that it can provide to them while they are trying to design their own CNN architectures. For instance, and according to the first coding trial, the initial speed of just one MAC unit can reach 3.5 Giga Operations per Second (GOPS) and has the ability to multiply up to 4 different inputs beside a common weight value, which will lead to a revolution in the FPGA capabilities for adopting the era of deep learning algorithms especially if we take in our consideration that also the blocks can work in parallel mode which can lead to increasing the data throughput of the proposed project to about 16 Tera Operations per Second (TOPS). Finally, we believe that this proposed CNN block for FPGA is just the first step that will leave no areas for competitions with the conventional CPUs and GPUs due to the massive speed that it can provide and its flexible scalability that it can be achieved from the parallelism concept of operation of such FPGA-based CNN blocks. | ||||||||||
| Boostdsp | 9 | 6 years ago | apache-2.0 | VHDL | ||||||
| VHDL Library for implementing common DSP functionality. | ||||||||||
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