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A simple implementation of a UART modem in Verilog.

Deep Darkfantasy ⭐ 15

Global Dark Mode for ALL apps on ANY platforms.

Hdl Deflate ⭐ 12

FPGA implementation of deflate (de)compress RFC 1950/1951

Openxc7 Tetrisaraj ⭐ 7

Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented with SW in the bare-metal 'C' they, together, make for this classic game. Except that it's now, in the standard BiH tradition, with a twist of our own.

Viterbi Decoder In Verilog ⭐ 6

An efficient implementation of the Viterbi decoding algorithm in Verilog

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