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44 search results found

VUnit is a unit testing framework for VHDL/SystemVerilog

Pyverilog ⭐ 567

Python-based Hardware Design Processing Toolkit for Verilog HDL

Various HDL (Verilog) IP Cores

NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network

Veriloggen ⭐ 275

Veriloggen: A Mixed-Paradigm Hardware Construction Framework

Vscode Verilog Hdl Support ⭐ 266

HDL support for VS Code

Async_fifo ⭐ 173

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Image Processing ⭐ 123

Image Processing Toolbox in Verilog using Basys3 FPGA

32 Verilog Mini Projects ⭐ 121

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SP

A complete open-source design-for-testing (DFT) Solution

Simulating Verilog designs on a microcontroller

Verugent ⭐ 46

Verilog generation tool written in Rust

Higan Verilog ⭐ 33

This is a higan/Verilator co-simulation example/framework

Riscv_cpu ⭐ 30

A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL

A simple implementation of a UART modem in Verilog.

8bit_microcomputer_verilog ⭐ 25

This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.

Spiking Neural Network On Fpga ⭐ 18

Leaky Integrate and Fire (LIF) model implementation for FPGA

Digital Flow ⭐ 18

This is a tutorial on standard digital design flow

Verilog Starter Tutorials ⭐ 17

Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.

Deep Darkfantasy ⭐ 15

Global Dark Mode for ALL apps on ANY platforms.

Getting Started With Verilog ⭐ 12

Verilog modules for beginners

Hdl Deflate ⭐ 12

FPGA implementation of deflate (de)compress RFC 1950/1951

Verilog_compiler ⭐ 12

Verilog_Compiler is now available in GitHub Marketplace! This tool can quickly compile Verilog code and check for errors, making it an essential tool for developers.

Hacktoberfest ⭐ 12

This Repository invites freelancer friendly neighbourhood developers to contribute to open source .

100daysofrtl ⭐ 12

"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

JAMMA Custom Arcade Project

Fpga_spi ⭐ 11

Connecting FPGA and Arduino using SPI.

Fpga Bicubic Interpolation ⭐ 10

use Verilog HDL implemente bicubic interpolation in FPGA

Mips Processor ⭐ 10

5-stage pipelined 32-bit MIPS microprocessor in Verilog

Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface

A Tcl-Library for scripted HDL generation

Ethernet Design Verilog ⭐ 8

Gigabit Ethernet UDP communication driver

Goldschmidt_integer_divider_parallel ⭐ 8

A Goldschmidt integer divider written in verilog. Similar to Newton-Raphson but the divison step can be pipelined.

8bit Computer ⭐ 8

Simple 8-bit computer build in Verilog

Openxc7 Tetrisaraj ⭐ 7

Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented with SW in the bare-metal 'C' they, together, make for this classic game. Except that it's now, in the standard BiH tradition, with a twist of our own.

Ece241_verilog ⭐ 7

This repo contains all the Verilog HDL files that I made during the course.

100daysof_rtl ⭐ 7

The Repository contains the code of various Digital Circuits

Motion_estimation_processor_fullsearch ⭐ 7

Fullsearch based Motion Estimation Processor written in Verilog-HDL

Bhg_i2c_init_rs232_debugger ⭐ 6

A Verilog I2C initializer with integrated RS232 debugger. *** New v1.1 Supports I2C CLK stretch and separate IO buffers for driving Efinix's IO primitive.

Viterbi Decoder In Verilog ⭐ 6

An efficient implementation of the Viterbi decoding algorithm in Verilog

Riscv32_beluga ⭐ 6

c compiler beluga with riscv32 backend

Riscv Isa Ci ⭐ 5

CI/CD for RISC-V Cores

Nocrouter ⭐ 5

👶🏻 My first baby steps into the world of NoC

Single Cycle Cpu ⭐ 5

Single-Cycle CPU

1-44 of 44 search results

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