Bhg_i2c_init_rs232_debugger
A Verilog I2C initializer with integrated RS232 debugger. *** New v1.1 Supports I2C CLK stretch and separate IO buffers for driving Efinix's IO primitive.
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
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| Fpga Application Development And Simulation | 96 | a year ago | 1 | mit | SystemVerilog | |||||
| 《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS). | ||||||||||
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| Ov7670_nexys4_verilog | 14 | 6 years ago | apache-2.0 | Verilog | ||||||
| This code is used to connect the OV7670 Camera to a NEXYS4 and then display the image on a monitor in Verilog | ||||||||||
| Upduino | 11 | 5 years ago | 1 | Verilog | ||||||
| Dvp_to_udp | 11 | 3 years ago | gpl-3.0 | Verilog | ||||||
| Uncompressed video uver UDP using 1000BASE-T Ethernet on Cyclone IV FPGA | ||||||||||
| Oc I2c | 10 | 13 years ago | Verilog | |||||||
| I2C controller core from Opencores.org | ||||||||||
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