Verugent
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Silice | 1,199 | 3 months ago | 73 | other | C++ | |||||
| Silice is an open source language that simplifies prototyping and writing algorithms on FPGA architectures. | ||||||||||
| J1sc | 72 | a year ago | bsd-3-clause | Scala | ||||||
| A reimplementation of a tiny stack CPU | ||||||||||
| Verugent | 46 | 10 months ago | 4 | January 22, 2020 | 1 | apache-2.0 | Rust | |||
| Verilog generation tool written in Rust | ||||||||||
| Cpu32 | 26 | 10 years ago | Verilog | |||||||
| Tiny MIPS for Terasic DE0 | ||||||||||
| Icebreaker Candy | 24 | 5 years ago | 1 | gpl-3.0 | Verilog | |||||
| Eye candy from an iCEBreaker FPGA and a 64×64 LED panel | ||||||||||
| Fpga_threelevelstorage | 23 | 4 years ago | gpl-3.0 | Coq | ||||||
| 【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。 | ||||||||||
| Hdmi To Fpga To Apa102 Pixels | 17 | 4 years ago | Verilog | |||||||
| Final Project written in Lucid (verilog) for the Mojo FPGA development board. Reads pixels from HDMI and sends pixel data to 22,000 APA102 LEDs over SPI. | ||||||||||
| Ws2812 Core | 17 | 3 years ago | Verilog | |||||||
| verilog core for ws2812 leds | ||||||||||
| Verilog_tutorials_bb | 16 | 8 years ago | Verilog | |||||||
| verilog tutorials for iCE40HX8K Breakout Board | ||||||||||
| Upduino V2.1 | 15 | 4 years ago | 3 | mit | Verilog | |||||
| UPduino | ||||||||||
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