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Search results for rtl xilinx
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xilinx
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24 search results found
Openwifi Hw
⭐
560
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
Nontrivial Mips
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362
NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
Fpga_readings
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249
Recipe for FPGA cooking
Libsystemctlm Soc
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175
SystemC/TLM-2.0 Co-simulation framework
Fpga Sdcard Reader
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142
An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器,可以从FAT16或FAT32格式的SD卡中读取文件。
Logic
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121
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Fpga Sdcard Reader Spi
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52
An FPGA-based SD-card reader via SPI bus, which can read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器(通过SPI总线),可以从FAT16或FAT32格式的SD卡中读取文件。
Bigpulp
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48
⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
Pyxsi
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46
Python/C/RTL cosimulation with Xilinx's xsim simulator
Hyperram
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39
Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
Hwtlib
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33
hardware library for hwt (= ipcore repo)
Fifo
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18
Generic FIFO implementation with optional FWFT
Virtio
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18
Virtio implementation in SystemVerilog
Xilinx_fpga_hls Mapping Neural Network To Hardware
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14
At present, just an example to show how to map the detection algorithm YOLOv2 from model to FPGA
Awesome Fpga List
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12
A collection of some awesome public FPGA projects.
Digital Hardware Modelling
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11
Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
Hdl Modules
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10
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
Cpu
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9
MIPS CPU
Pymtl Tut Hls
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8
Tutorial for integrating PyMTL and Vivado HLS
Zet86
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8
Zet - The x86 (IA-32) open implementation
Kvcordic
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8
Multi-function, universal, fixed-point CORDIC
Openxc7 Tetrisaraj
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7
Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented with SW in the bare-metal 'C' they, together, make for this classic game. Except that it's now, in the standard BiH tradition, with a twist of our own.
Systolicarray
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6
A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.
Gost 28147 89
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5
Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher
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