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Search results for risc v soc

22 search results found

Vexriscv ⭐ 2,135

A FPGA friendly 32 bit RISC-V CPU implementation

Chipyard ⭐ 1,393

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Neorv32 ⭐ 1,337

🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Riscv Cores List ⭐ 791

RISC-V Cores, SoC platforms and SoCs

E203_hbirdv2 ⭐ 741

The Ultra-Low Power RISC-V Core

Riscv_vhdl ⭐ 552

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

Pulp Dronet ⭐ 428

A deep learning-powered visual navigation engine to enables autonomous navigation of pocket-size quadrotor - running on PULP

A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

Ustc Rvsoc ⭐ 261

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

Saxonsoc ⭐ 133

SoC based on VexRiscv and ICE40 UP5K

Tang_e203_mini ⭐ 103

LicheeTang 蜂鸟E203 Core

Nuclei Sdk ⭐ 91

Nuclei RISC-V Software Development Kit

K210 Hal ⭐ 63

Rust's hardware abstract layer (HAL) for K210 chip, a dual RV64GC SoC with hardware accelerated AI peripherals. Contributions welcomed!

Icebreaker Litex Examples ⭐ 57

Example litex Risc-V SOC and some example code projects in multiple languages.

Riscy Soc ⭐ 54

Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog

The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.

Firechip ⭐ 46

Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.

Neorv32 Setups ⭐ 44

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations

Axi Crossbar ⭐ 38

An AXI4 crossbar implementation in SystemVerilog

website of hellollvm.org

Riscv Soc Cores ⭐ 23

Platform Shakti ⭐ 22

Shakti: development platform for PlatformIO

Zephyr Riscv ⭐ 20

Zephyr port to riscv architecture

Picorv32_xilinx ⭐ 19

A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz

Picorv32_tang ⭐ 18

A 32-bit RISC-V SoC on FPGA that supports RT-Thread.

Systemoncat ⭐ 17

An SoC with multiple RISC-V IMA processors.

Azadi Soc ⭐ 16

Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.

Riscv Atom ⭐ 14

An open-source 32-bit RISC-V soft-core processor for FPGAs.

L2 R6: WCH 120MHz RISC-V3A USB3.0 SoC (CH569)

L1 R1：WCH RISC-V4A BLE SoC (CH583/CH582/CH581)

Riscv_soc ⭐ 10

Basic RISC-V Test SoC

De10 Nano Riscv ⭐ 7

A RISC-V SoC ( Hbird e203 ) on Terasic DE10-Nano

BOOM's Simulation Accelerator.

L2 R2: WCH RISC-V BLE SoC (CH573/CH571)

Fpga_test_soc ⭐ 5

A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)

Riscv_verilator_model ⭐ 5

RISCV model for Verilator/FPGA targets

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1-22 of 22 search results

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