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Search results for matlab verilog
matlab
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verilog
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16 search results found
Fp23fftk
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31
Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).
Fpga_qpsk Modem
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26
A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA
Hust Lab
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22
Labs for Computer Science - c, asm, data structure, csapp, hsi, matlab, digital logic, verilog, compilers, operating systems
Design And Verification Of Ldpc Decoder
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17
- Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and parallel architecture. - Created modules for all variants of the variable node unit(VNU) and the check-node unit(CNU) based on the H matrix. Created script for module instantiation of VNU and CNU as per the H matrix. - Verified the functionality of the Verilog implementation by self-checking test-bench in Verilog to compare the results with Matlab.
Math
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15
Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)
Ofdm_802_11
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11
32 Point Fft Verilog Design Based Dit Butterfly Algorithm
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10
This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clock domains and time-shared design
Verilog Fir
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9
FIR implemention with Verilog
Gem_project
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9
There are the documents, floating and fixed-point algorithms, and Verilog codes for the project.
Tsinghua Ee Miscellanea
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8
🐾 Miscellanious projects during 2014-2018 in Dept. of Electronic Engineering, Tsinghua University
Hdc Language Recognition
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6
Hyperdimensional computing for language recognition: Matlab and RTL implementations
Microshift_compression
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6
Microshift Compression: An Efficient Image Compression Algorithm for Hardware
Cic_prune
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6
A C version of Rick Lyon's Matlab implementation of Hogenauer's CIC filter register pruning algorithm
802.11a
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5
Software-Hardware Implementation of IEEE 802.11a Wifi Standard
Drfm
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5
Code for paper entitled "Low Cost FPGA based Implementation of a DRFM System"
Blackman_harris_win
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5
Blackman-Harris Window functions (3-, 5-, 7-term etc.) from 1K to 64M points based only on LUTs and DSP48s FPGA resources. Main core - CORDIC like as DDS (sine / cosine generator)
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1-16 of 16 search results
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