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Search results for haskell verilog
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verilog
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16 search results found
Clash Compiler
⭐
1,336
Haskell to VHDL/Verilog/SystemVerilog compiler
Bsc
⭐
850
Bluespec Compiler (BSC)
Sv2v
⭐
429
SystemVerilog to Verilog conversion
Reduceron
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296
FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to
Verismith
⭐
89
Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
Blarney
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86
Haskell library for hardware description
Clash Riscv
⭐
30
A RiscV processor implementing the RV32I instruction set written in Clash
Haski
⭐
30
Cλash/Haskell FPGA-based SKI calculus evaluator
Netlist Verilog
⭐
16
Netlist and Verilog Haskell Package
Clash Yosys Demo
⭐
10
Deploying Haskell to Lattice iCE40 using fully open source toolchain
Finlog
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9
Compiling finite generators to digital logic. WIP
Icfp2020_bluespec_tutorial
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9
Tutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference
Mips Simulator
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9
💻 A 5-stage pipeline MIPS CPU design in Haskell.
Pipelinedsl
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9
Haskell DSL for describing hardware pipelines
Enigma_cryptol_bluespec_bsv
⭐
7
Modeling the WW2 Enigma crypto machine in Cryptol and Bluespec BSV
Clash Pong
⭐
6
Pong in Haskell / Clash, running as software using SDL and as hardware targeting FPGAs
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1-16 of 16 search results
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