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Search results for fpga parallelism

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Yolov2_xilinx_fpga ⭐ 624

A demo for accelerating YOLOv2 in xilinx's fpga pynq/zedboard

Reduceron ⭐ 296

FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to

Opencl Fpga Examples ⭐ 6

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