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The Top 23 Fpga Asic Open Source Projects

Open source projects categorized as Fpga Asic
Categories > Hardware > Asic
Categories > Hardware > Fpga
Cva6 ⭐ 2,042
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
most recent commit a month ago
Clash Compiler ⭐ 1,336
Haskell to VHDL/Verilog/SystemVerilog compiler
total releases 87most recent commit 3 months ago
Serv ⭐ 1,158
SERV - The SErial RISC-V CPU
most recent commit 4 months ago
Fusesoc ⭐ 1,065
Package manager and build abstraction tool for FPGA/ASIC development
dependent packages 5total releases 26most recent commit 3 months agopypi fusesoc} Downloads
Axi ⭐ 834
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
most recent commit 4 months ago
Riscv Cores List ⭐ 791
RISC-V Cores, SoC platforms and SoCs
most recent commit 3 years ago
Vunit ⭐ 678
VUnit is a unit testing framework for VHDL/SystemVerilog
dependent packages 5total releases 87most recent commit 25 days agopypi vunit-hdl} Downloads
Embedded Neural Network ⭐ 547
collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning
most recent commit 3 months ago
Riscv ⭐ 364
RISC-V CPU Core (RV32IM)
most recent commit 3 years ago
Poc ⭐ 324
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
most recent commit 4 years ago
Cores ⭐ 302
Various HDL (Verilog) IP Cores
most recent commit 3 years ago
Biriscv ⭐ 300
32-bit Superscalar RISC-V CPU
most recent commit 3 years ago
Esp ⭐ 267
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
most recent commit 4 months ago
Rggen ⭐ 261
Code generation tool for configuration and status registers
total releases 62most recent commit 3 months ago
Surf ⭐ 259
A huge VHDL library for FPGA development
most recent commit 5 months ago
Aes ⭐ 238
Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
most recent commit a year ago
Tensil ⭐ 218
Open source machine learning accelerators
most recent commit 2 years ago
Systemrdl Compiler ⭐ 212
SystemRDL 2.0 language compiler front-end
dependent packages 14total releases 50most recent commit 3 months agopypi systemrdl-compiler} Downloads
Livehd ⭐ 192
Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
total releases 4most recent commit 3 months ago
Async_fifo ⭐ 173
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
most recent commit a year ago
Ztachip ⭐ 172
Opensource software/hardware platform to build edge AI solutions deployed on FPGA or custom ASIC hardware.
most recent commit 3 months ago
Mflowgen ⭐ 169
mflowgen -- A Modular ASIC/FPGA Flow Generator
total releases 6most recent commit 3 months ago
Open Register Design Tool ⭐ 169
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
most recent commit 9 months ago
The 7 Most Depended On Fpga Asic Open Source Projects
Systemrdl Compiler ⭐ 212
SystemRDL 2.0 language compiler front-end
dependent packages 14total releases 50latest release November 09, 2023most recent commit 3 months agopypi systemrdl-compiler} Downloads
Fusesoc ⭐ 1,065
Package manager and build abstraction tool for FPGA/ASIC development
dependent packages 5total releases 26latest release November 17, 2023most recent commit 3 months agopypi fusesoc} Downloads
Vunit ⭐ 678
VUnit is a unit testing framework for VHDL/SystemVerilog
dependent packages 5total releases 87latest release April 23, 2023most recent commit 25 days agopypi vunit-hdl} Downloads
Dfiant ⭐ 56
DFiant: A Dataflow Hardware Descripition Language
dependent packages 4total releases 3latest release September 05, 2023most recent commit 7 months ago
Peakrdl ⭐ 48
Control and status register code generator toolchain
dependent packages 4total releases 11latest release October 26, 2023most recent commit 6 months agopypi peakrdl} Downloads
Peakrdl Ipxact ⭐ 29
Import and export IP-XACT XML register models
dependent packages 2total releases 17latest release August 31, 2023most recent commit 6 months agopypi peakrdl-ipxact} Downloads
Pygears ⭐ 93
HW Design: A Functional Approach
dependent packages 1total releases 21latest release October 28, 2018most recent commit 2 years agopypi pygears} Downloads
The 10 Latest Releases In Fpga Asic Open Source Projects
Fusesoc ⭐ 1,065
Package manager and build abstraction tool for FPGA/ASIC development
dependent packages 5total releases 26latest release November 17, 2023most recent commit 3 months agopypi fusesoc} Downloads
Clash Compiler ⭐ 1,336
Haskell to VHDL/Verilog/SystemVerilog compiler
total releases 87latest release November 11, 2023most recent commit 3 months ago
Systemrdl Compiler ⭐ 212
SystemRDL 2.0 language compiler front-end
dependent packages 14total releases 50latest release November 09, 2023most recent commit 3 months agopypi systemrdl-compiler} Downloads
Peakrdl ⭐ 48
Control and status register code generator toolchain
dependent packages 4total releases 11latest release October 26, 2023most recent commit 6 months agopypi peakrdl} Downloads
Rggen ⭐ 261
Code generation tool for configuration and status registers
total releases 62latest release October 18, 2023most recent commit 3 months ago
Peakrdl Regblock ⭐ 36
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
total releases 20latest release October 12, 2023most recent commit 4 months ago
Mflowgen ⭐ 169
mflowgen -- A Modular ASIC/FPGA Flow Generator
total releases 6latest release September 21, 2023most recent commit 3 months ago
Dfiant ⭐ 56
DFiant: A Dataflow Hardware Descripition Language
dependent packages 4total releases 3latest release September 05, 2023most recent commit 7 months ago
Peakrdl Ipxact ⭐ 29
Import and export IP-XACT XML register models
dependent packages 2total releases 17latest release August 31, 2023most recent commit 6 months agopypi peakrdl-ipxact} Downloads
Vunit ⭐ 678
VUnit is a unit testing framework for VHDL/SystemVerilog
dependent packages 5total releases 87latest release April 23, 2023most recent commit 25 days agopypi vunit-hdl} Downloads
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