Project Name	Stars	Most Recent Commit	Open Issues	License	Language
Finlog	9	4 years ago		bsd-3-clause	Haskell
Compiling finite generators to digital logic. WIP
Tizzy	6	13 years ago	1	other	Python
Graphviz dot to Verilog Finite State Machine (FSM) generator written in Python
Fpga	5	9 years ago			Verilog
related to Spartan6 FPGA

Alternatives To Fpga

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Finlog ⭐ 9

Compiling finite generators to digital logic. WIP

most recent commit 4 years ago

Tizzy ⭐ 6

Graphviz dot to Verilog Finite State Machine (FSM) generator written in Python

most recent commit 13 years ago

Fpga ⭐ 5

related to Spartan6 FPGA

most recent commit 9 years ago

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