| loykylewong/FPGA-Application-Development-and-Simulation |
96 |
|
0 |
0 |
almost 3 years ago |
0 |
|
1 |
mit |
SystemVerilog |
| 《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS). |
| Kirill888/parallella-fpga-dummy-io |
35 |
|
0 |
0 |
about 10 years ago |
0 |
|
0 |
|
Tcl |
| Sample minimal Vivado project for Parallella FPGA |
| ZipCPU/wbi2c |
35 |
|
0 |
0 |
over 2 years ago |
0 |
|
0 |
|
Verilog |
| Wishbone controlled I2C controllers |
| Archfx/FPGA-stereo-Camera-Basys3 |
22 |
|
0 |
0 |
over 3 years ago |
0 |
|
0 |
|
Verilog |
| Integration of two camera modules to Basys 3 FPGA |
| mattvenn/fpga-virtual-graf |
21 |
|
0 |
0 |
over 7 years ago |
0 |
|
1 |
|
Verilog |
| robseb/HPS2FPGAmapping |
21 |
|
0 |
0 |
about 5 years ago |
0 |
|
1 |
mit |
Verilog |
| SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V) |
| MLAB-project/Modules |
15 |
|
0 |
0 |
over 2 years ago |
0 |
|
3 |
gpl-3.0 |
G-code |
| MLAB hardware modules and building blocks |
| jonlwowski012/OV7670_NEXYS4_Verilog |
14 |
|
0 |
0 |
over 7 years ago |
0 |
|
0 |
apache-2.0 |
Verilog |
| This code is used to connect the OV7670 Camera to a NEXYS4 and then display the image on a monitor in Verilog |
| bitflippersanonymous/fpga-camera |
10 |
|
0 |
0 |
over 13 years ago |
0 |
|
0 |
gpl-3.0 |
VHDL |
| FPGA digital camera controller and frame capture device in VHDL |
| Archfx/FPGA-DepthMap-Basys3 |
8 |
|
0 |
0 |
over 3 years ago |
0 |
|
1 |
mit |
VHDL |
| Real Time depth map generation using SSD algorithm on low end Basys 3 FPGA. Support 320x240 and 160x120 resolutions. |
