Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
---|---|---|---|---|---|---|---|---|---|---|
Vortex | 939 | 4 months ago | 51 | apache-2.0 | Verilog | |||||
Z3 | 111 | 9 years ago | bsd-3-clause | C | ||||||
A Verilog implementation of the Infocom Z-Machine V3. With BIOS and benchmarks. Verified in hardware. | ||||||||||
Benchmarks | 102 | a year ago | 2 | mit | Verilog | |||||
EPFL logic synthesis benchmarks | ||||||||||
Manthan | 26 | 8 months ago | 1 | other | Python | |||||
Manthan for Boolean function synthesis | ||||||||||
Hdl Benchmarks | 18 | 4 months ago | 4 | other | Verilog | |||||
Collection of open HDL modules, subsystems and microprocessors (benchmarks) that are used for related tools testing. | ||||||||||
Opdb | 18 | a year ago | Verilog | |||||||
OpenPiton Design Benchmark | ||||||||||
Datc_robust_design_flow | 15 | 4 years ago | 2 | gpl-3.0 | Verilog | |||||
DATC Robust Design Flow. | ||||||||||
Rdf 2019 | 14 | 4 years ago | mit | Verilog | ||||||
DATC RDF | ||||||||||
Yosys Bench | 12 | 4 years ago | 4 | isc | Verilog | |||||
Benchmarks for Yosys development | ||||||||||
Md5cracker | 10 | 9 years ago | Verilog | |||||||
A Hardware MD5 Cracker for the Cyclone V SoC |