Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
---|---|---|---|---|---|---|---|---|---|---|
Vexriscv | 2,135 | 6 months ago | 100 | mit | Assembly | |||||
A FPGA friendly 32 bit RISC-V CPU implementation | ||||||||||
Neorv32 | 1,337 | 5 months ago | 15 | bsd-3-clause | VHDL | |||||
🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. | ||||||||||
Riscv_vhdl | 552 | 6 months ago | 2 | apache-2.0 | Verilog | |||||
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators | ||||||||||
Forth Cpu | 276 | 2 years ago | VHDL | |||||||
A Forth CPU and System on a Chip, based on the J1, written in VHDL | ||||||||||
W11 | 109 | a year ago | 13 | gpl-3.0 | VHDL | |||||
PDP-11/70 CPU core and SoC | ||||||||||
Zpu | 104 | 9 years ago | VHDL | |||||||
The Zylin ZPU | ||||||||||
Tpu | 82 | 8 years ago | 1 | VHDL | ||||||
TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. Designed to run on miniSpartan6+. | ||||||||||
J1sc | 72 | 2 years ago | bsd-3-clause | Scala | ||||||
A reimplementation of a tiny stack CPU | ||||||||||
Rpu | 70 | 4 years ago | apache-2.0 | VHDL | ||||||
Basic RISC-V CPU implementation in VHDL. | ||||||||||
Bit Serial | 65 | 10 months ago | mit | VHDL | ||||||
A bit-serial CPU written in VHDL, with a simulator written in C. |