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Search results for rtl yosys
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4 search results found
Openlane
⭐
1,148
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Sphinxcontrib Hdl Diagrams
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43
Sphinx Extension which generates various types of diagrams from Verilog code.
Openxc7 Tetrisaraj
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7
Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented with SW in the bare-metal 'C' they, together, make for this classic game. Except that it's now, in the standard BiH tradition, with a twist of our own.
Digsim
⭐
7
An interactive digital logic simulator with verilog support (Yosys)
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