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yosys
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49 search results found
Openlane
⭐
1,148
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Cariboulite
⭐
1,005
CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR
Nmigen
⭐
589
A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
Edalize
⭐
573
An abstraction library for interfacing EDA tools
Netlistsvg
⭐
567
draws an SVG schematic from a JSON netlist
Sv2v
⭐
429
SystemVerilog to Verilog conversion
Caravel
⭐
223
Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.
Eurorack Pmod
⭐
137
Hardware and gateware for getting started in FPGA-based audio synthesis with open source tools.
Caravel_mpw One
⭐
130
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
Yodl
⭐
96
A VHDL frontend for Yosys
Fpga Tool Perf
⭐
90
FPGA tool performance profiling
Ecp5 Pcie
⭐
83
Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe
Yosys F4pga Plugins
⭐
81
Plugins for Yosys developed as part of the F4PGA project.
Xcrypto
⭐
80
XCrypto: a cryptographic ISE for RISC-V
Doppler
⭐
61
Arduino compatible – Cortex M4F & FPGA Development Board
Yosys
⭐
57
Unofficial Yosys WebAssembly packages
Psl_with_ghdl
⭐
54
Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
Neorv32 Setups
⭐
44
📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
Sphinxcontrib Hdl Diagrams
⭐
43
Sphinx Extension which generates various types of diagrams from Verilog code.
Linuxcnc Rio
⭐
42
RealtimeIO for LinuxCNC based on an FPGA
Tangnano9k Series Examples
⭐
37
Examples for the Lushay Labs tang nano 9k series
Docker
⭐
34
Scripts to build and use docker images including GHDL
Fpga Sdft
⭐
32
sliding DFT for FPGA, targetting Lattice ICE40 1k
Pyfpga
⭐
31
A Python package to use FPGA development tools programmatically.
Eda_tools
⭐
24
A Dockerfile with a collections of ready to use open source EDA tools: Yosys, SimbiYosys (with Z3, boolector and Yices2), nextpnr-ice40, netxpnr-ecp5, nextpnr-gowin, Amaranth HDL, Silice and Verilator.
Formal_hw_verification
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23
Trying to verify Verilog/VHDL designs with formal methods and tools
Hdx
⭐
21
[mirror] HDL development environment on Nix.
Padring
⭐
19
A padring generator for ASICs
Enigmafpga
⭐
18
Enigma in FPGA
Scarv Cpu
⭐
18
SCARV: a side-channel hardened RISC-V platform
5a 75b Tools
⭐
14
a collection of tools made while messing with the Colorlight 5A-75B V7.0 and some notes using ECP5 with Yosys
Risc8
⭐
13
Mostly AVR compatible FPGA soft-core
Yosys Tcl Ui Report
⭐
12
5 Day TCL begginer to advanced training workshop by VSD
Croyde Riscv
⭐
10
A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
Ibex Yosys Build
⭐
10
Testing Ibex build using Yosys and open source toolchains.
Verifying Foss Hdl Synthesizers
⭐
10
a project to check the FOSS synthesizers against vendors EDA tools
Doppler Fpga Firmware
⭐
10
Bitstream src for doppler
Fusesoc_template
⭐
10
Example of how to get started with olofk/fusesoc.
Gatemate_experiments
⭐
9
Experiments with Cologne Chip's GateMate FPGA architecture
Openxc7 Tetrisaraj
⭐
7
Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented with SW in the bare-metal 'C' they, together, make for this classic game. Except that it's now, in the standard BiH tradition, with a twist of our own.
Digsim
⭐
7
An interactive digital logic simulator with verilog support (Yosys)
Xc9500
⭐
6
WIP open source tooling for the XC9500 / XC9500XL series of CPLDs from Xilinx.
Upduino Example
⭐
6
Example UPduino project setup for Linux, macOS and WIndows+WSL for synthesis and simulation
Ulx3s Blinky
⭐
5
A blinky project for the ULX3S v3.0.3 FPGA board
Yosys Vscode
⭐
5
Syntax Highlighting for Yosys Scripts and RTLIL
Opensource Embeded Toolchains
⭐
5
Embeded Toolchains in opensource way
Doppler4arduino
⭐
5
Arduino board package for doppler (SAMD51 Cortex M4F + ICE40up5K FPGA)
Torii Hdl
⭐
5
A modern hardware definition language and toolchain based on Python
Icicle
⭐
5
An OSS CAD Suite Version Manager
Related Searches
Verilog Yosys (33)
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