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18 search results found
Openlane
⭐
1,148
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Axi
⭐
834
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Cores
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302
Various HDL (Verilog) IP Cores
Esp
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267
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
Rggen
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261
Code generation tool for configuration and status registers
Surf
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259
A huge VHDL library for FPGA development
Open Register Design Tool
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169
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
Tekno Kizil
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129
KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi
Logic
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121
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Verilog Parser
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68
A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.
Hdlgen
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60
HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve
Vga Clock
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33
Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
Design And Asic Implementation Of 32 Point Fft Processor
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20
I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of a
Gatery
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14
Gatery, a library for circuit design.
Hdl Modules
⭐
10
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
Vsdstdcelldesign
⭐
9
This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedures on how to create a custom LEF file and plugging it into an openlane flow.
Peakrdl Verilog
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8
Generate verilog register file from systemRDL description
Gost 28147 89
⭐
5
Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher
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