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29 search results found

Tinyfpga Bootloader ⭐ 304

An open source USB bootloader for FPGAs

Code generation tool for configuration and status registers

Verilog ⭐ 243

Repository for basic (and not so basic) Verilog blocks with high re-use potential

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

Systemrdl Compiler ⭐ 212

SystemRDL 2.0 language compiler front-end

Open Register Design Tool ⭐ 169

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Fastvdma ⭐ 92

Antmicro's fast, vendor-neutral DMA IP in Chisel

Haskell library for hardware description

A collection of MyHDL cores and tools for complex digital circuit design

Control and status register code generator toolchain

Small Processing Unit 32: A compact RV32I CPU written in Verilog

Peakrdl Uvm ⭐ 41

Generate UVM register model from compiled SystemRDL input

Peakrdl Html ⭐ 40

Generate address space documentation HTML from compiled SystemRDL input

Peakrdl Regblock ⭐ 36

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

Xark's Open Source Embedded Retro Adapter - FPGA based video for rosco_m68k and others

Python script for programming the iCEBlink40 development board under linux

Fpgammix ⭐ 24

Partial implementation of Knuth's MMIX processor (FPGA softcore)

Mecrisp Ice ⭐ 17

http://mecrisp.sourceforge.net/ Mecrisp-Ice is an enhanced version of Swapforth and the J1a stack processor by James Bowman, featuring three MSP430 style IO ports, a tick counter, constant folding, inlining and tail-call optimisations

Tang Nano_tetris ⭐ 17

Tetris on Tang-Nano FPGA

Ics Adpcm ⭐ 16

Programmable multichannel ADPCM decoder for FPGA

Mostly AVR compatible FPGA soft-core

16 bit RISC-V proof of concept

Fpganes_release ⭐ 11

Reconstructing NES game console on Altera DE1-SOC FPGA using System Verilog

FPGA firmware for FPGA radio baseband board. Scroll down for README.

Nes_fpga ⭐ 10

An NES emulator on a Cyclone IV FPGA.

Usrp Pid Controller ⭐ 8

The purpose of this project is to use the USRP1, an FPGA with a convenient analog front manufactured by ettus research ( http://www.ettus.com/ ), as a PID Feedback controller. The project provides a custom fpga bit file which allows the USRP1 to be used for this purpose, as well as a python-based user interface.

Fpga_flappy_bird ⭐ 7

🐦 a simple hardware-implementation of the viral game "Flappy Bird" built for use on the Digilent NEXYS 2 Development Board (XC3S500E-FG320)

Regenerate ⭐ 7

Manages registers for ASIC and FPGA designs

Tang Nano_midi_sounder ⭐ 7

Core_audio ⭐ 5

Audio controller (I2S, SPDIF, DAC)

Sap 1 V2 Mojo ⭐ 5

SAP-1 CPU in Verilog for the Mojo FPGA board - has seperate address bus.

Tang Nano_partyparrot ⭐ 5

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1-29 of 29 search results

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