Awesome Open Source
Search
Programming Languages
Languages
All Categories
Categories
About
Search results for asic hdl
asic
x
hdl
x
19 search results found
Surf
⭐
259
A huge VHDL library for FPGA development
Tensil
⭐
218
Open source machine learning accelerators
Livehd
⭐
192
Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
Async_fifo
⭐
173
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
Logic
⭐
121
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Pygears
⭐
93
HW Design: A Functional Approach
Hdlgen
⭐
60
HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve
Dfiant
⭐
56
DFiant: A Dataflow Hardware Descripition Language
Hdlab Fpga Development Board
⭐
43
Open source FPGA development platform
My Verilog Examples
⭐
22
A place to keep my synthesizable verilog examples.
Svlogger
⭐
11
SystemVerilog Logger
Mastering Fpgasic Book
⭐
8
📖 Mastering FPGASIC Book
Spinalhdl Template
⭐
8
Mill template for beginning your SpinalHDL project
Wrapped_rgb_mixer
⭐
7
Demo project for the Zero to ASIC Course.
Apogeorv
⭐
6
A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.
Libsv
⭐
6
An open source, parameterized SystemVerilog digital hardware IP library
Frequency_counter
⭐
6
Project 2.2 Frequency counter
Gost 28147 89
⭐
5
Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher
Tinyuart
⭐
5
Lightweight UART core in VHDL
Related Searches
Fpga Asic (109)
Verilog Hdl (98)
Fpga Hdl (92)
1-19 of 19 search results
Privacy
|
About
|
Terms
|
Follow Us On Twitter
Copyright 2018-2024 Awesome Open Source. All rights reserved.