Project Name	Stars	Packages Using This	Most Recent Commit	Total Releases	Latest Release	Open Issues	License	Language
Opentimer	368		a year ago			48	other	Verilog
A High-performance Timing Analysis Tool for VLSI Systems
Circuitgraph	74	1	a year ago	7	September 24, 2021	11	mit	Verilog
Tools for working with circuits as graphs in python
Hdelk	50		2 years ago			7	apache-2.0	JavaScript
Web-based HDL diagramming tool
Yahdl	15		6 years ago			2	bsd-3-clause	Java
A programming language for FPGAs.
Netlist Graph	8		7 years ago				mit	Java
Java library for parsing and manipulating graph representations of gate-level Verilog netlists
Sparkfun Rgb Bar Graph	6		10 months ago					Verilog

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Opentimer ⭐ 368

A High-performance Timing Analysis Tool for VLSI Systems

most recent commit a year ago

Circuitgraph ⭐ 74

Tools for working with circuits as graphs in python

dependent packages 1total releases 7most recent commit a year ago

Hdelk ⭐ 50

Web-based HDL diagramming tool

most recent commit 2 years ago

Yahdl ⭐ 15

A programming language for FPGAs.

most recent commit 6 years ago

Netlist Graph ⭐ 8

Java library for parsing and manipulating graph representations of gate-level Verilog netlists

most recent commit 7 years ago

Sparkfun Rgb Bar Graph ⭐ 6

most recent commit 10 months ago

Suggest An Alternative To netlist-graph

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Netlist Graph vs Opentimer

Netlist Graph vs Circuitgraph

Netlist Graph vs Hdelk

Netlist Graph vs Yahdl

Netlist Graph vs Sparkfun Rgb Bar Graph

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