Cryptohdl
A list of VHDL codes implementing cryptographic algorithms
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Neotrng | 113 | 6 months ago | bsd-3-clause | VHDL | ||||||
| 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC). | ||||||||||
| Simon_speck_ciphers | 61 | 6 years ago | 1 | July 21, 2018 | mit | VHDL | ||||
| Implementations of the Simon and Speck Block Ciphers | ||||||||||
| Spinalcrypto | 36 | 2 years ago | 2 | mit | Scala | |||||
| SpinalHDL - Cryptography libraries | ||||||||||
| Cryptohdl | 13 | 2 years ago | 1 | gpl-3.0 | VHDL | |||||
| A list of VHDL codes implementing cryptographic algorithms | ||||||||||
| Cryptocores | 11 | 3 years ago | gpl-2.0 | VHDL | ||||||
| cryptography ip-cores in vhdl / verilog | ||||||||||
| Hw Sike | 6 | 4 years ago | cc0-1.0 | VHDL | ||||||
| FPGA implementation of the Supersingular Isogeny Key Encapsulation | ||||||||||
| Code Portfolio | 5 | 3 years ago | apache-2.0 | C | ||||||
| Code Portfolio -- Collection of Interesting CS and ECE Projects in different languages (C, C++, Python, CPU & GPU Parallel Paradigms, MATLAB, and VHDL) and target hardware with technical reports, and my Vim Config | ||||||||||
| Rsa_security_token | 5 | 7 years ago | bsd-3-clause | VHDL | ||||||
| A Security token system for (two-factor) authentication to Linux / Unix using an FPGA and a PAM-module. Either A: 72-bit or B: 512-bit RSA. Version A is air-gapped. Version B uses USB UART. BSD-3 licensed. | ||||||||||
| Yaaes | 5 | 3 years ago | 1 | lgpl-3.0 | VHDL | |||||
| Yet Another AES implementation in hardware. | ||||||||||
| Grain 128aead Vhdl | 5 | 5 years ago | VHDL | |||||||
| The VHDL reference implementation along with optimized versions of the stream cipher Grain-128AEAD | ||||||||||
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