Turborav

A self-contained computer stack hobby project
Alternatives To Turborav
Project NameStarsDownloadsRepos Using ThisPackages Using ThisMost Recent CommitTotal ReleasesLatest ReleaseOpen IssuesLicenseLanguage
Leflow329
4 years ago1otherVerilog
Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks
Iob Soc131
3 months ago8mitVerilog
RISC-V System on Chip Template
Ice Chips Verilog99
a year ago4gpl-3.0Verilog
IceChips is a library of all common discrete logic devices in Verilog
Fpga Odysseus58
6 months agoVerilog
FPGA Odysseus with ULX3S
Fuxi40
3 years agogpl-3.0Verilog
Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
Usb Test Suite Build35
3 years ago4apache-2.0Shell
Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
Dram Bender21
7 months ago1mitVHDL
DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art DDR4 modules of different form factors. Five prototypes are available on different FPGA boards. Described in our preprint: https://arxiv.org/pdf/2211.05838.pdf
Bluecheck21
3 years agootherBluespec
A generic test bench written in Bluespec
Libvhdl19
2 years agootherVHDL
Library of reusable VHDL components
Virtio18
6 years ago1apache-2.0SystemVerilog
Virtio implementation in SystemVerilog
Alternatives To Turborav
Select To Compare


Alternative Project Comparisons
Popular Testing Projects
Popular Fpga Projects
Popular Software Quality Categories

Get A Weekly Email With Trending Projects For These Categories
No Spam. Unsubscribe easily at any time.
Testing
Scala
Fpga