Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
---|---|---|---|---|---|---|---|---|---|---|
Leflow | 329 | 4 years ago | 1 | other | Verilog | |||||
Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks | ||||||||||
Iob Soc | 131 | 3 months ago | 8 | mit | Verilog | |||||
RISC-V System on Chip Template | ||||||||||
Ice Chips Verilog | 99 | a year ago | 4 | gpl-3.0 | Verilog | |||||
IceChips is a library of all common discrete logic devices in Verilog | ||||||||||
Fpga Odysseus | 58 | 6 months ago | Verilog | |||||||
FPGA Odysseus with ULX3S | ||||||||||
Fuxi | 40 | 3 years ago | gpl-3.0 | Verilog | ||||||
Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3. | ||||||||||
Usb Test Suite Build | 35 | 3 years ago | 4 | apache-2.0 | Shell | |||||
Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores | ||||||||||
Dram Bender | 21 | 7 months ago | 1 | mit | VHDL | |||||
DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art DDR4 modules of different form factors. Five prototypes are available on different FPGA boards. Described in our preprint: https://arxiv.org/pdf/2211.05838.pdf | ||||||||||
Bluecheck | 21 | 3 years ago | other | Bluespec | ||||||
A generic test bench written in Bluespec | ||||||||||
Libvhdl | 19 | 2 years ago | other | VHDL | ||||||
Library of reusable VHDL components | ||||||||||
Virtio | 18 | 6 years ago | 1 | apache-2.0 | SystemVerilog | |||||
Virtio implementation in SystemVerilog |