Cgra_pnr
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Vtr Verilog To Routing | 925 | 4 months ago | 447 | other | C++ | |||||
| Verilog to Routing -- Open Source CAD Flow for FPGA Research | ||||||||||
| Rapidstream | 85 | a year ago | 4 | mit | Python | |||||
| [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs. | ||||||||||
| P4fpga | 46 | 6 years ago | 11 | bsd-2-clause | Bluespec | |||||
| P4-14/16 Bluespec Compiler | ||||||||||
| Icefloorplan | 21 | 6 years ago | 1 | other | C++ | |||||
| iCE40 floorplan viewer | ||||||||||
| Rapidstream | 19 | 2 years ago | 5 | mit | Python | |||||
| [FPGA 2022] Parallel placement and routing of Vivado HLS dataflow designs. | ||||||||||
| Cgra_pnr | 14 | | 1 | 1 | 2 years ago | 35 | August 28, 2022 | C++ | ||
| Fast PnR toolchain for CGRA | ||||||||||
| Study Materials | 12 | a year ago | mit | |||||||
| Awesome Eda | 9 | 5 years ago | ||||||||
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