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Search results for vivado
vivado
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77 search results found
Hls4ml
⭐
1,104
Machine learning on FPGAs using HLS
Fpga
⭐
1,103
帮助大家进行FPGA的入门,分享FPGA相关的优秀文章,优秀项目
Hdmi
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892
Send video/audio over HDMI on an FPGA
Prjxray
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731
Documenting the Xilinx 7-series bit-stream format.
Vivado Risc V
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682
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
Edalize
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573
An abstraction library for interfacing EDA tools
Vscode Verilog Hdl Support
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266
HDL support for VS Code
Rapidwright
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262
Build Customized FPGA Implementations for Vivado
Lenet5_hls
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188
FPGA Accelerator for CNN using Vivado HLS
Image Processing
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123
Image Processing Toolbox in Verilog using Basys3 FPGA
Logic
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121
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Tinytpu
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111
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
Vivado On Silicon Mac
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102
Installs Vivado on M1/M2 macs
Rapidstream
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85
[FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
Limago
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83
Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack
Cnn_for_slr
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79
A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.
Vhdl Course
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58
VHDL course at Brno University of Technology
Zedboard Tutorial
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58
Vivado+PetaLinux 系统搭建教程 —— 基于 Zedboard
Intfftk
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56
Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
Rc Fpga Zcu
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43
Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
Fixed Floating Point Adder Multiplier
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42
16-bit Adder Multiplier hardware on Digilent Basys 3
Hyperram
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33
Portable HyperRAM controller
Prjuray
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33
Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
Pyfpga
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31
A Python package to use FPGA development tools programmatically.
Arm Legv8
⭐
29
Verilog Implementation of an ARM LEGv8 CPU
Innova2_flex_xcku15p_notes
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29
Nvidia/Mellanox Innova-2 Flex Open Programmable SmartNIC Setup and Usage Notes for XCKU15P FPGA Development
Custom_part_data_files
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28
Xilinx PCIe to MIG DDR4 example designs and custom part data files
Fpga_qpsk Modem
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26
A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA
Hwac_object_tracker
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24
FPGA accelerated TinyYOLO v2 object detection neural network
Scoreboard Wtimer
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23
Objective of this project was to emulate a Basketball scoreboard, with timer and two teams scores. See readme for pic and more details. FPGA design with Vivado.
My Verilog Examples
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22
A place to keep my synthesizable verilog examples.
Ebaz4205
⭐
22
Vivado and PetaLinux projects for Zynq EBAZ4205 Board
Openhbmc
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21
Open-source high performance AXI4-based HyperRAM memory controller
Eda Scripts
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20
Collect of various scripts for helping work with EDA-tools (ASIC, FPGA, etc)
Rapidstream
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19
[FPGA 2022] Parallel placement and routing of Vivado HLS dataflow designs.
Virtio
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18
Virtio implementation in SystemVerilog
Vivado Docker
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16
Dockerfile with Vivado for CI
Vdt Plugin
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15
mirror of https://git.elphel.com/Elphel/vdt-plugin
Tcl_for_fpga
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15
TCL scripts for FPGA (Xilinx)
Deep Darkfantasy
⭐
15
Global Dark Mode for ALL apps on ANY platforms.
Sha256hasher
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15
SHA-256 IP core for ZedBoard (Zynq SoC)
Pothoszynq
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14
DMA source and sink blocks for Xilinx Zynq FPGAs
F4pga Xc7 Bram Patch
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12
Tool for updating the contents of BlockRAMs found in Xilinx 7 series bitstreams.
Fpga Miner
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12
💰 A simplified version of an FPGA bitcoin miner 💰
Vivado
⭐
12
🧛🏻♂️ Dark theme for Vivado
Ics 2021spring Fdu
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11
Introduction to Computer Systems (II), Spring 2021.
Rules_vivado
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11
Bazel rules for Xilinx Vivado
Svreal
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11
Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
Verifying Foss Hdl Synthesizers
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10
a project to check the FOSS synthesizers against vendors EDA tools
Fusesoc_template
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10
Example of how to get started with olofk/fusesoc.
Hdl Modules
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10
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
Mnist_hls
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10
Lenet for MNIST handwritten digit recognition using Vivado hls tool
Comet
⭐
10
RISC-V ISA based 32-bit processor written in HLS
Ultra96 Fractal
⭐
9
Hardware accelerated Julia set explorer running on Ultra96
Noop Lo
⭐
9
A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.
Innova2_xcku15p_ddr4_bram_gpio
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9
XDMA PCIe to DDR4 and GPIO and BRAM for the Innova-2 Flex XCKU15P FPGA
Hdlgen Chatgpt
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9
HDLGen-ChatGPT, works in tandem with ChatGPT-3.5 chat interface to enable fast digital systems design and test specification capture, and automatic generation of both VHDL and Verilog models, and testbenches, and AMD Vivado and Intel Quartus Electronic Design Automation (EDA) project
Hardware Implementation Of The Canny Edge Detection Algorithm
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9
The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient to replicate using any simulator and any of the available FPGA boards, including those from Xilinx and Altera.
Pynq_dma
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8
PYNQ DMA benchmark project
Vivado Wrapper
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8
Wrap vivado as a simple project manager, which works in shell command line natively.
Merlin
⭐
8
Learn how to create your own 32-bit system from scratch.
Lv_port_xilinx_zedboard_vitis
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8
This repository contains a template AMP project for the Zedboard using VGA, FreeRTOS, LVGL and USB peripherals
Xilinx Reports Plugin
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7
A Jenkins plugin for reporting FPGA utilization
Barebonescortexm0
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7
Extremely basic CortexM0 SoC based on ARM DesignStart Eval
F4pga Xc Fasm2bels
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6
Library to convert a FASM file into BELs importable into Vivado.
Tinyml Zybo
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6
This repository is a collection of designs invloving FPGAs and AI technologies.
Ibertpy
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6
A Python package for running IBERT Eye scan in Vivado, ploting eye diagrams with mathplotlib and compiling results with LaTeX
Zybo Linux
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6
A complete Linux project for the ZYBO. This project helps me during my first steps with embedded Linux. You can find anything necessary to run your own embedded Linux on your ZYBO here.
Applied_digital_logic_exercises_using_fpgas
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6
Selected projects from "Applied Digital Logic Exercises using FPGAs", by Kurt Wick.
Hdu_co_guide
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6
HDU Computer Organization Course Design Beginner Guide - 杭电计组课设新手指南
Hi Dmm
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6
Hi-DMM: High-Performance Dynamic Memory Management in HLS (High-Level Synthesis)
Zcu102_two_cameras
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5
ZCU102 two IMX274 camera design.
Make Fpga
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5
Set of scripts for Vivado's project handling
Fsearch
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5
FastSearch is a project intended to increase the speed of string searching by using the FPGA technology
Visual System Integrator
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5
Visual System Integrator - Accelerate your embedded development
Anppv_risc_pipelinedprocessor
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5
Mips 32bit
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5
Four versions of MIPS 32bit implemented in Verilog using Vivado, ready for Simulation and Nexys4 DDR Board
Related Searches
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