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5 search results found
Openlane
⭐
1,148
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Crash_course_for_new_members
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26
Deep Learning & VLSI Crash Course for New Members
Rdf 2019
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14
DATC RDF
Gatery
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14
Gatery, a library for circuit design.
Digital Hardware Modelling
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11
Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
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