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Search results for c plus plus fpga
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fpga
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193 search results found
Cgra_pnr
⭐
14
Fast PnR toolchain for CGRA
Iob Versat
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14
Coarse Grained Reconfigurable Array
Metalfs
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14
Near-storage compute aware file system and FPGA operator pipelines.
Gatery
⭐
14
Gatery, a library for circuit design.
Celex4 Opalkelly
⭐
13
SDK for CeleX4 sensor.
Fpga_bitonicsorting
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13
Implementation of BitonicSorting algorithm on FPGA through SDAccel using Opencl as source code
Gpstudio
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13
Toolchain for FPGA-based smart camera by Dream Team IP
Boyi
⭐
13
A systematic framework for optimizing OpenCL applications on FPGAs (FPGA'20)
Telscale Ss7card
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13
Temporary repo of OpenSigtran project
Arcade Centipede_mister
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13
Arcade: Centipede
Lattuino_ip_core
⭐
13
An Arduino UNO compatible implementation for the iCE40 FPGAs
Daphne Benchmark
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12
The Darmstadt Automotive Parallel HeterogeNEous (DAPHNE) Benchmark-Suite
Imagedetectionhw2
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12
HOG + SVM on FPGA
Iir Bandstop Filter
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12
Implementation of pipelined IIR bandstop filter in Verilog, C++ and MATLAB with fixed point arithmetic
Fpga_lecture
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12
Source Codes for a lecture entitled "Parallel and Reconfigurable VLSI Computing" in Tokyo Tech.
Rasterix
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12
OpenGL 1.x implementation for FPGAs
Fpga_cpfp
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12
HLS Custom-Precision Floating-Point Library
Bil
⭐
12
Bitfile Interpretation Library for Xilinx Virtex FPGAs
Aws F1 Developer Labs
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12
AWS F1 Xilinx Developer Labs
Solvercodegen
⭐
12
C++ code generation tools for real-time CPU or FPGA simulation solvers of electrical and power electronic systems
Cask
⭐
11
Generate and tune custom architectures for sparse linear algebra
Ics 2021spring Fdu
⭐
11
Introduction to Computer Systems (II), Spring 2021.
Openvino With Fpga Hello World Face Detection
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11
Arch2019_assignment
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11
Logisticregression
⭐
11
Logistic regression FPGA core
Finance.zynqpricer.hls
⭐
11
Heston implementation for Zynq with Vivado HLS
32 Point Fft Verilog Design Based Dit Butterfly Algorithm
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10
This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clock domains and time-shared design
Rpi Jtag Spartan3
⭐
10
Raspberry PI JTAG programmer for Spartan3 FPGA.
Fireprog
⭐
10
A tool for configuring Xilinx Spartan 3 FPGAs via FT232H-based USB-to-JTAG adapter
Galapagos
⭐
10
Mtcnn_with_hls_on_fpga
⭐
10
MTCNN with convolution reprogramed in c
C Ll Verilog
⭐
10
An LLVM based mini-C to Verilog High-level Synthesis tool
Hls_ldpc_dec
⭐
9
Full piplined LDPC decoder (IEEE 802.16e) implement in FPGA using Xilinx HLS(C synthesis to Verilog Codes)..
Dach
⭐
9
DaCH: dataflow cache for high-level synthesis.
Ultra96 Fractal
⭐
9
Hardware accelerated Julia set explorer running on Ultra96
Lm8
⭐
9
A custom 8-bit computer and software suite
Fwmpy
⭐
9
A multiply core generator
Opencv Fpga
⭐
9
FPGA-supported OpenCV Prototype (Added new FPGA OpenCV module, modified opencv-core to support Altera FPGA callstream)
Nios_duino
⭐
9
NIOSDuino - Arduino framework running on NIOS II
Aws Fpga Simple Example
⭐
9
A simple example of using the SDAccel build flow for AWS EC2's F1 instance type. Trys to avoid magic makefiles.
Yosys Bluespec
⭐
8
Yosys plugin for synthesis of Bluespec code
Xvc Adaptive
⭐
8
Xilinx Virtual Cable (XVC) daemon with calibration features
Ml Kws For Fpga
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8
https://github.com/ARM-software/ML-KWS-for-MCU
Mico32
⭐
8
LatticeMico32 instruction set simulator project
Xf Fusion
⭐
8
提出了一种新的红外与可见光图像融合算法,并基于zynq搭建了图像融合应用。
Knn
⭐
8
Lin Analyzer
⭐
8
A high-level performance analysis tool for FPGA-based accelerators
The Thing Fpga Stm32
⭐
8
"The Thing": Cyclone II FPGA + Arduino STM32F103C8T6 board, Multicomp compatible.
Virtualization Emulation Guide
⭐
8
Virtualization/Emulation Guide
Clink
⭐
8
Compact LSTM inference kernel (CLINK) designed in C/HLS for FPGA implementation.
Db Fx Strategy
⭐
8
Roll model for trading strategy to C++ or FPGA via Matlab tool
Mechatronics Software
⭐
8
mechatronics software
Riscv
⭐
8
32-bit soft RISCV processor for FPGA applications
Seti_fpga
⭐
7
Port of SETI@Home to an FPGA Platform
Stream Fpga
⭐
7
Implementation of the STREAM benchmark for FPGA
Zybo
⭐
7
Miscellaneous things and projects for my ZYBO and ZYNQ devices.
Entity Block
⭐
7
Creates a .SVG symbol from a VHDL entity. Colors and some other properties can be adjusted.
Core_sdram_axi4
⭐
7
SDRAM controller with AXI4 interface
Hls_arbitrary_precision_types
⭐
7
Vdf Fpga Round2 Results
⭐
7
Frd Cv Demo Pedestrian Detection
⭐
7
Phi
⭐
7
Hardware description language that tries not to suck
Olswinloader
⭐
7
Windows program for updating the Open Logic Sniffer FPGA flash ROM
Pif2
⭐
7
FPGA on a 40-pin Raspberry Pi
Slam
⭐
7
SLAM dissertation project
Vhde
⭐
7
VHDL Diagram Editor
Alexnet Fpga Implementation
⭐
7
This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.
Fpga_pcie_drivers
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6
FPGA_PCIe_drivers
Neuralfpga
⭐
6
Sharpmz
⭐
6
A Sharp MZ Series (80K,80C,1200,80A,80B,700,800,2000) Computer Hardware Emulation written in VHDL on Altera FPGA fabric. Runs on the MiSTer project and other Altera Cyclone devices.
Vhdlsonic
⭐
6
A custom 32-bit architecture, microcontroller, retro console, and software suite
Protonvm
⭐
6
Parallel Bytecode Interpreter For Heterogeneous Hardware
Kria_yolov3_ppe
⭐
6
Xilinx Kria KV260 Real-time PPE detection
Drm
⭐
6
Accelize DRM, a solution to secure and monetize FPGA design or IP
Sme Developer Labs
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6
Zybotr2 96 Fpt19
⭐
6
An UGV-system using SoC-FPGA developed for FPGA design competition held on ICFPT2019
Pynq Rtl Sdr
⭐
6
A FPGA accelerated SDR receiver using PYNQ-Z2 board and RTL-SDR
Alcha
⭐
6
A New Programming Language for FPGA Projects
Faiss Fpga
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6
An FPGA integration and acceleration of the popular FAISS framework for approximate similarity search
Polygon Gouraud_shading
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6
polygon sample of Gouraud shading.
Coursera Sdaccel Theory
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6
Source codes used during the Coursera course titled "Developing FPGA-accelerated cloud applications with SDAccel: Theory"
Chai Fpga
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6
Collaborative Execution Strategies for Heterogeneous CPU-FPGA Architectures
Qwave Project
⭐
5
FPGA development board with DSO module
Smartcamera_opencl_de1soc
⭐
5
This project contains code developed by a research team at University of Colorado,Boulder and Embry Riddle Aeronautical University to explore FPGA and GP-GPU co-processor power efficiency for continous transform 3D mapping and sensor fusion. Please use at your own risk. We are sharing so that other researchers and developers can recreate our results and make suggestions to improve and extend the benchmarks over time. The results we obtained were documented in the SPIE Sensor and Technologies p
Programming Books
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5
This is a list of programming books that I have read.
Openreroc_motion_sensor
⭐
5
OpenReroc (Open Reconfigurable Robot Component) Motion Sensor
Openreroc_pwm
⭐
5
OpenReroc (Open Reconfigurable Robot Component) pwm
Jt5205
⭐
5
Verilog ADPCM decoder compatible with OKI MSM5205
Fpga Sha256
⭐
5
Acceleration of SHA256 on the AWS F1 instance using OpenCL.
Slamdunk
⭐
5
Coursera Sdaccel Practice
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5
source codes used during the Coursera course titled "Developing FPGA-accelerated cloud applications with SDAccel: Practice"
Suite 16
⭐
5
Logic design, schematics and code for 16-bit TTL computer based on 4-bit slice
Coldboot
⭐
5
Hardware Accelerated Cold-Boot Attacks
Libudmaio
⭐
5
Userspace I/O library for Xilinx AXI S2MM DMA
Adaptive_component
⭐
5
A composable container for Adaptive ROS 2 Node computations. Select between FPGA, CPU or GPU at run-time.
Zynq7 Sdr
⭐
5
Software defined radio receiver on the Zynq7 SoC
Pattern Viewer
⭐
5
FPGA에서 사용되는 pat파일 컴파일러에 대한 패턴 뷰어프로그램입니다.
Ustc Rv Chisel
⭐
5
Chisel implementation of USTC RISC-V
Pifz
⭐
5
FPGA on a Raspberry PiZero
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