Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
---|---|---|---|---|---|---|---|---|---|---|
Darkriscv | 1,795 | 5 months ago | 9 | bsd-3-clause | Verilog | |||||
opensouce RISC-V cpu core implemented in Verilog from scratch in one night! | ||||||||||
Pipelinec | 519 | 3 months ago | 82 | gpl-3.0 | Python | |||||
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature. | ||||||||||
Leros | 87 | 5 months ago | 3 | bsd-2-clause | VHDL | |||||
A Tiny Processor Core | ||||||||||
P4fpga | 46 | 6 years ago | 11 | bsd-2-clause | Bluespec | |||||
P4-14/16 Bluespec Compiler | ||||||||||
Siafpgaminer | 44 | 6 years ago | 1 | mit | VHDL | |||||
VHDL FPGA design of an optimized Blake2b pipeline to mine Siacoin | ||||||||||
Risc V Cpu | 34 | 6 years ago | 1 | Verilog | ||||||
RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL. | ||||||||||
Kyogenrv | 25 | 3 years ago | apache-2.0 | Scala | ||||||
The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA. | ||||||||||
Hls Cnn | 19 | 4 months ago | mit | C | ||||||
High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition. | ||||||||||
Metalfs | 14 | 2 years ago | 3 | mit | C++ | |||||
Near-storage compute aware file system and FPGA operator pipelines. | ||||||||||
Bitmap Vhdl Package | 9 | 6 years ago | n,ull | mit | VHDL | |||||
A vhdl package for reading and writing bitmap files. |