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Search results for altera
altera
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41 search results found
Basic_verilog
⭐
1,333
Must-have verilog systemverilog modules
Hdmi
⭐
892
Send video/audio over HDMI on an FPGA
Edalize
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573
An abstraction library for interfacing EDA tools
F32c
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390
A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz
Poc
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324
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
Openfpgaduino
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135
All open source file and project for OpenFPGAduino project
Haasoscope
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107
Docs, design, firmware, and software for the Haasoscope
Hftrx
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68
Embedded firmware for ham radio transceivers
C5soc_opencl
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65
DE1SOC DE10-NANO DE10-Standard OpenCL hardware that support VGA and desktop. And Some applications such as usb camera YUYV to RGB , Sobel and so on.
Intfftk
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56
Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
Vim Hdl
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53
Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)
Ixo Usb Jtag
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47
usb-jtag - Altera USB Blaster Emulation with a FX2
Brianhg Ddr3 Controller
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34
DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
Hyperram
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33
Portable HyperRAM controller
Fp23fftk
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31
Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).
Pyfpga
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31
A Python package to use FPGA development tools programmatically.
Fpga Speech Recognition
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28
Expiremental Speech Recognition System using VHDL & MATLAB.
Kyogenrv
⭐
25
The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
Hps2fpgamapping
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21
SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)
Fpga Docker
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20
Tools for running FPGA vendor toolchains with Docker
Mark_ii
⭐
20
Simple SoC in VHDL with full toolchain and custom board.
Verilog Fpga
⭐
19
Many peripherals in Verilog ready to use
Meta Intelfpga
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16
Yocto Project BSP meta-layer for Intel (ALTERA) SoC-FPGAs (SoCFPGA) - with step by step guide
Zalt
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14
Zalt is a home brew Z80 computer with a modern(isch) chipset.
Spectrum
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12
Spectrum analyzer system using a 512-point FFT, in a Cyclone IV FPGA. Reads i2s audio from the codec and then does all FFT/VGA functions. Nios just reads the FFT result and draws the display bars. VGA frame buffer on-chip. VGA signals generated on-chip. See the included video files to watch it in action.
Fpga Mandelbrot
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11
FPGA mandelbrot accelerator via high speed/super speed USB
Alterajtaguart
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11
Altera JTAG UART wrapper for Bluespec
Hdl Modules
⭐
10
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
Quickspi
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9
Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
Jniosemu
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9
JNiosEmu is an educational Nios II based development environment and emulator with the purpose of making it easy to learn programming in assembler. Assemble your source with a single button click, immediately see how values change in a register or memory. All this without any prior knowledge of assembler programming or complex tool chains.
Max2 Audio Dac
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9
24-bit Stereo Audio DAC for Raspberry Pi
Mastering Fpgasic Book
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8
📖 Mastering FPGASIC Book
Redphone Pcb
⭐
7
Simple handmade open source mobile phone
De10 Nano Riscv
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7
A RISC-V SoC ( Hbird e203 ) on Terasic DE10-Nano
Fpga_riscv_cpu
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6
fpga verilog risc-v rv32i cpu
Red_tracker
⭐
6
Uses the D8M camera module, then processes the image to detect red objects, and then overlay an x,y crosshair on the largest red object. See the video. Pure Verilog. (No soft-core processor.)
Django2fpgademo
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6
Demonstration how to build a Management Web interface to interact with the FPGA fabric and change the FPGA configuration with the Django Framework
Mastermind
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5
FPGA implementation of the popular logic game using VHDL and Altera DE1
Gost 28147 89
⭐
5
Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher
Awesome Fpga Boards
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5
Second life for FPGA boards which can be repurposed
Arp
⭐
5
RISC-V based microprocessor system for Altera DE0 FPGA board
1-41 of 41 search results
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