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The Top 10 Verilog Yosys Open Source Projects
Open source projects categorized as Verilog Yosys
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The-OpenROAD-Project/OpenLane
⭐
1,091
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
dependent packages
0
total releases
0
most recent commit
over 2 years ago
olofk/edalize
⭐
573
An abstraction library for interfacing EDA tools
dependent packages
0
total releases
0
most recent commit
over 2 years ago
zachjs/sv2v
⭐
429
SystemVerilog to Verilog conversion
dependent packages
0
total releases
0
most recent commit
over 2 years ago
efabless/caravel
⭐
223
Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.
dependent packages
0
total releases
0
most recent commit
over 2 years ago
apfelaudio/eurorack-pmod
⭐
137
Hardware and gateware for getting started in FPGA-based audio synthesis with open source tools.
dependent packages
0
total releases
0
most recent commit
over 2 years ago
efabless/caravel_mpw-one
⭐
130
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
dependent packages
0
total releases
0
most recent commit
over 4 years ago
chipsalliance/yosys-f4pga-plugins
⭐
81
Plugins for Yosys developed as part of the F4PGA project.
dependent packages
0
total releases
0
most recent commit
over 2 years ago
scarv/xcrypto
⭐
80
XCrypto: a cryptographic ISE for RISC-V
dependent packages
0
total releases
0
most recent commit
over 3 years ago
dadamachines/doppler
⭐
61
Arduino compatible – Cortex M4F & FPGA Development Board
dependent packages
0
total releases
0
most recent commit
about 7 years ago
stnolting/neorv32-setups
⭐
44
📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
dependent packages
0
total releases
0
most recent commit
over 2 years ago
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