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The Top 23 Verilog Hdl Open Source Projects

Open source projects categorized as Verilog Hdl
Categories > Hdl
Categories > Hardware > Verilog
Hdl ⭐ 1,299
HDL libraries and projects
most recent commit 3 months ago
Metroboy ⭐ 1,088
A repository of gate-level simulators and tools for the original Game Boy.
most recent commit 2 months ago
Awesome Hdl ⭐ 830
Hardware Description Languages
most recent commit 3 months ago
Bsv_tutorial_cn ⭐ 381
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开
most recent commit 7 months ago
Pymtl3 ⭐ 344
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
dependent packages 2total releases 30most recent commit 22 days agopypi pymtl3} Downloads
Sv Tests ⭐ 257
Test suite designed to check compliance with the SystemVerilog standard.
most recent commit a month ago
F4pga Arch Defs ⭐ 245
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
most recent commit a month ago
Kaze ⭐ 193
An HDL embedded in Rust.
total releases 20most recent commit 5 months ago
Async_fifo ⭐ 173
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
most recent commit a year ago
Fomu Workshop ⭐ 148
Support files for participating in a Fomu workshop
most recent commit a year ago
Metron ⭐ 143
A C++ to Verilog translation tool with some basic guarantees that your code will work.
most recent commit 3 months ago
Cpu11 ⭐ 142
Revengineered ancient PDP-11 CPUs, originals and clones
most recent commit 4 months ago
Hdl_checker ⭐ 136
Repurposing existing HDL tools to help writing better code
total releases 20most recent commit 2 years ago
Open5g_phy ⭐ 135
A ressource efficient, customizable, synthesizable 5G NR lower PHY written in Verilog
most recent commit 8 months ago
Logic ⭐ 121
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
most recent commit 4 years ago
Symbolator ⭐ 73
HDL symbol generator
total releases 3most recent commit 4 years ago
J1sc ⭐ 72
A reimplementation of a tiny stack CPU
most recent commit a year ago
Hdlgen ⭐ 60
HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve
most recent commit 6 months ago
Hdl Tools ⭐ 60
Facilitates building open source tools for working with hardware description languages (HDLs)
most recent commit 4 years ago
Sol 1 ⭐ 57
Sol-1: A CPU/Computer System made from 74 series logic.
most recent commit 4 months ago
Hdelk ⭐ 50
Web-based HDL diagramming tool
most recent commit 2 years ago
Sphinxcontrib Hdl Diagrams ⭐ 43
Sphinx Extension which generates various types of diagrams from Verilog code.
dependent packages 1total releases 9most recent commit 7 months agopypi sphinxcontrib-hdl-diagrams} Downloads
Brianhg Ddr3 Controller ⭐ 34
DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
most recent commit 2 years ago
The 5 Most Depended On Verilog Hdl Open Source Projects
Vcd ⭐ 32
Value Change Dump (VCD) parser
dependent packages 3total releases 27latest release March 12, 2023most recent commit 3 months agonpm vcd-stream} Downloads
Reqack ⭐ 23
🔁 elastic circuit toolchain
dependent packages 2total releases 37latest release May 20, 2020most recent commit 2 years agonpm reqack} Downloads
Pymtl3 ⭐ 344
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
dependent packages 2total releases 30latest release November 02, 2023most recent commit 22 days agopypi pymtl3} Downloads
Sphinxcontrib Hdl Diagrams ⭐ 43
Sphinx Extension which generates various types of diagrams from Verilog code.
dependent packages 1total releases 9latest release September 21, 2023most recent commit 7 months agopypi sphinxcontrib-hdl-diagrams} Downloads
The 10 Latest Releases In Verilog Hdl Open Source Projects
Pymtl3 ⭐ 344
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
dependent packages 2total releases 30latest release November 02, 2023most recent commit 22 days agopypi pymtl3} Downloads
Py4hw ⭐ 7
Hardware Design/Visualization/Simulation/RTLGeneration Framework
total releases 11latest release October 05, 2023most recent commit 4 months ago
Sphinxcontrib Hdl Diagrams ⭐ 43
Sphinx Extension which generates various types of diagrams from Verilog code.
dependent packages 1total releases 9latest release September 21, 2023most recent commit 7 months agopypi sphinxcontrib-hdl-diagrams} Downloads
Xeda ⭐ 30
Cross EDA Abstraction and Automation
total releases 34latest release July 26, 2023most recent commit 4 months ago
Vcd ⭐ 32
Value Change Dump (VCD) parser
dependent packages 3total releases 27latest release March 12, 2023most recent commit 3 months agonpm vcd-stream} Downloads
Libsv ⭐ 6
An open source, parameterized SystemVerilog digital hardware IP library
total releases 3latest release January 31, 2022most recent commit 2 years ago
Hdl_checker ⭐ 136
Repurposing existing HDL tools to help writing better code
total releases 20latest release August 14, 2021most recent commit 2 years ago
Kaze ⭐ 193
An HDL embedded in Rust.
total releases 20latest release March 14, 2021most recent commit 5 months ago
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