Lakeroad
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Dsp Theory | 792 | a year ago | 1 | gpl-3.0 | Jupyter Notebook | |||||
| Theory of digital signal processing (DSP): signals, filtration (IIR, FIR, CIC, MAF), transforms (FFT, DFT, Hilbert, Z-transform) etc. | ||||||||||
| Notes | 365 | 4 years ago | 4 | HTML | ||||||
| 研究生阶段的一些文章（技术、思考、读书笔记、日常琐事等） | ||||||||||
| Ua3reo Ddc Transceiver | 293 | 4 months ago | 9 | gpl-3.0 | C | |||||
| DDC/DUC SDR Tranceiver project | ||||||||||
| Fxpmath | 154 |  | 3 | 4 months ago | 23 | April 24, 2022 | 15 | mit | Python | |
| A python library for fractional fixed-point (base 2) arithmetic and binary manipulation with Numpy compatibility. | ||||||||||
| Maia Sdr | 144 |  | 2 | 6 months ago | 4 | September 29, 2023 | 1 | Python | ||
| Maia SDR is an open-source FPGA-based SDR project focusing on the ADALM Pluto | ||||||||||
| Dspfilters | 119 | 4 months ago | 1 | Verilog | ||||||
| A collection of demonstration digital filters | ||||||||||
| Ice40_ultraplus_examples | 115 | 2 years ago | 3 | mpl-2.0 | Verilog | |||||
| Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation | ||||||||||
| Pyrpl | 113 | 10 months ago | 4 | August 29, 2017 | 147 | mit | Python | |||
| pyrpl turns your RedPitaya into a powerful DSP device, especially suitable as a lockbox in quantum optics experiments. | ||||||||||
| Fpga Application Development And Simulation | 96 | 10 months ago | 1 | mit | SystemVerilog | |||||
| 《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS). | ||||||||||
| Caffepresso | 80 | 7 years ago | C | |||||||
| CaffePresso: An Optimized Library for Deep Learning on Embedded Accelerator-based platforms | ||||||||||
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