Project Name	Stars	Most Recent Commit	Open Issues	Language
Dpll	82	5 months ago		Verilog
A collection of phase locked loop (PLL) related projects
Antikernel	65	4 years ago	1	Verilog
The Antikernel operating system project
Deocmpldcv	8	5 years ago		VHDL
This project is a port of the 1chipMSX to DEOCM + DE0-CV including modification of OCM-PLD.
Pin Assignment For De10 Standard	6	5 years ago	1
FPGA实验用DE10-Standard开发板引脚表

Alternatives To Deocmpldcv

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Dpll ⭐ 82

A collection of phase locked loop (PLL) related projects

most recent commit 5 months ago

Antikernel ⭐ 65

The Antikernel operating system project

most recent commit 4 years ago

Deocmpldcv ⭐ 8

This project is a port of the 1chipMSX to DEOCM + DE0-CV including modification of OCM-PLD.

most recent commit 5 years ago

Pin Assignment For De10 Standard ⭐ 6

FPGA实验用DE10-Standard开发板引脚表

most recent commit 5 years ago

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Deocmpldcv vs Dpll

Deocmpldcv vs Antikernel

Deocmpldcv vs Pin Assignment For De10 Standard

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