Caravel_fpga250
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Trng | 26 | 4 years ago | bsd-2-clause | Verilog | ||||||
| True Random Number Generator core implemented in Verilog. | ||||||||||
| Caravel_fpga250 | 7 | 3 years ago | apache-2.0 | Verilog | ||||||
| FPGA250 aboard the eFabless Caravel | ||||||||||
| Verilog Buildingblocks | 6 | 4 years ago | lgpl-3.0 | Verilog | ||||||
| Library of generic verilog buildingblocks | ||||||||||
| Rautanoppa | 5 | 9 years ago | gpl-3.0 | Verilog | ||||||
| Hardware random number generator for FPGAs | ||||||||||
| Bist_puf_trng | 5 | 7 years ago | Verilog | |||||||
| A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators | ||||||||||
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