Fusionconverter
Design files for the open-hardware NeoGeo MVS to AES converter
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Aes | 238 | a year ago | 1 | bsd-2-clause | Verilog | |||||
| Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys. | ||||||||||
| Spinalcrypto | 36 | 2 years ago | 2 | mit | Scala | |||||
| SpinalHDL - Cryptography libraries | ||||||||||
| Cmac | 12 | a year ago | bsd-2-clause | Verilog | ||||||
| Implementation of the CMAC keyed hash function using AES as block cipher. | ||||||||||
| Fusionconverter | 12 | 2 years ago | 1 | gpl-2.0 | Verilog | |||||
| Design files for the open-hardware NeoGeo MVS to AES converter | ||||||||||
| Zynq Aes | 11 | 3 years ago | 1 | mit | C | |||||
| AES hardware engine for Xilinx Zynq platform | ||||||||||
| Cryptocores | 11 | 3 years ago | gpl-2.0 | VHDL | ||||||
| cryptography ip-cores in vhdl / verilog | ||||||||||
| Aes_chisel | 10 | 2 years ago | 2 | April 04, 2019 | apache-2.0 | Scala | ||||
| Implementation of the Advanced Encryption Standard in Chisel | ||||||||||
| Balsa Aes Core | 5 | 13 years ago | Verilog | |||||||
| Asynchronous AES core written using the Balsa hardware description language | ||||||||||
Alternatives To FusionconverterSelect To Compare
Alternative Project Comparisons
Popular Aes Projects
Popular Verilog Projects
Popular Security Categories
Related Searches
Get A Weekly Email With Trending Projects For These Categories
No Spam. Unsubscribe easily at any time.
Verilog
Pcb
Aes