Mks Sgen_l V2
MKS SGEN_L V2.0 is powerful 32-bit 3D printer control board. The CPU is LPC1769 120MHZ, SGEN_L V2 hardware Integrated 4KB EEPROM, 5AXIS and dual Z interface, has 2 way FANs and Dc12/24V out interface, support TMC UART and SPI mode...
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Inteltxe Poc | 394 | 4 years ago | 1 | Python | ||||||
| Intel Management Engine JTAG Proof of Concept | ||||||||||
| Oldland Cpu | 89 | 8 years ago | 1 | Verilog | ||||||
| Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools | ||||||||||
| Stm32 Ili9341 | 72 | 5 years ago | 8 | mit | C | |||||
| Simple HAL driver for ILI9341 320x240 TFT LCD with Touchscreen for STM32 microcontrollers | ||||||||||
| Mks Sgen_l V2 | 55 | 2 years ago | 17 | gpl-3.0 | C++ | |||||
| MKS SGEN_L V2.0 is powerful 32-bit 3D printer control board. The CPU is LPC1769 120MHZ, SGEN_L V2 hardware Integrated 4KB EEPROM, 5AXIS and dual Z interface, has 2 way FANs and Dc12/24V out interface, support TMC UART and SPI mode... | ||||||||||
| Mesabusprotocol | 13 | 7 years ago | Verilog | |||||||
| Flexible Byte transport protocol for bus bridging CPUs to FPGAs over UART,SPI,SERDES physical interfaces | ||||||||||
| Fpga_test_soc | 5 | 4 years ago | 1 | C | ||||||
| A small test SoC for various soft-CPUs (Cortex-M0, RISC-V) | ||||||||||
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