Project Name	Stars	Most Recent Commit	Open Issues	License	Language
Vexriscv	2,135	4 months ago	100	mit	Assembly
A FPGA friendly 32 bit RISC-V CPU implementation
Ghdl Yosys Plugin	270	7 months ago	28	gpl-3.0	VHDL
VHDL synthesis (based on ghdl)
Smartvhdl	11	8 months ago	5	apache-2.0	Python
SublimeText Plugin for VHDL (highlight, autocompletion, navigation, ...)
Linter Vhdl	5	3 years ago	3	mit	JavaScript
Atom vhdl linter
Hdl_plugin	5	13 years ago			VimL
Generate vhdl/verilog testbench file for vhdl files.

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Vexriscv ⭐ 2,135

A FPGA friendly 32 bit RISC-V CPU implementation

most recent commit 4 months ago

Ghdl Yosys Plugin ⭐ 270

VHDL synthesis (based on ghdl)

most recent commit 7 months ago

Smartvhdl ⭐ 11

SublimeText Plugin for VHDL (highlight, autocompletion, navigation, ...)

most recent commit 8 months ago

Linter Vhdl ⭐ 5

Atom vhdl linter

most recent commit 3 years ago

Hdl_plugin ⭐ 5

Generate vhdl/verilog testbench file for vhdl files.

most recent commit 13 years ago

Suggest An Alternative To linter-vhdl

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Linter Vhdl vs Vexriscv

Linter Vhdl vs Ghdl Yosys Plugin

Linter Vhdl vs Smartvhdl

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