Altera Sockit Hardcaml Alternatives
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Vexriscv | 2,135 | a year ago | 100 | mit | Assembly | |||||
| A FPGA friendly 32 bit RISC-V CPU implementation | ||||||||||
| Nyuziprocessor | 1,863 | a year ago | 90 | apache-2.0 | C | |||||
| GPGPU microprocessor architecture | ||||||||||
| Darkriscv | 1,795 | a year ago | 9 | bsd-3-clause | Verilog | |||||
| opensouce RISC-V cpu core implemented in Verilog from scratch in one night! | ||||||||||
| E200_opensource | 1,688 | 4 years ago | 33 | apache-2.0 | Verilog | |||||
| Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2 | ||||||||||
| Fromthetransistor | 1,607 | 3 years ago | 16 | |||||||
| From the Transistor to the Web Browser, a rough outline for a 12 week course | ||||||||||
| Neorv32 | 1,337 | a year ago | 15 | bsd-3-clause | VHDL | |||||
| 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. | ||||||||||
| Clash Compiler | 1,336 | 44 | a year ago | 87 | November 11, 2023 | 280 | other | Haskell | ||
| Haskell to VHDL/Verilog/SystemVerilog compiler | ||||||||||
| Hdl | 1,299 | a year ago | 54 | other | Verilog | |||||
| HDL libraries and projects | ||||||||||
| Zipcpu | 1,139 | a year ago | 4 | Verilog | ||||||
| A small, light weight, RISC CPU soft core | ||||||||||
| Platformio Vscode Ide | 1,104 |  | 2 | 2 | a year ago | 25 | February 04, 2022 | 175 | apache-2.0 | JavaScript |
| PlatformIO IDE for VSCode: The next generation integrated development environment for IoT | ||||||||||
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