Xilinx Deep Learning Nexys4

Implemented Darius IP (originally target PYNQ) of convolution and maxpool on Xilinx FPGA with SDK
Alternatives To Xilinx Deep Learning Nexys4
Project NameStarsDownloadsRepos Using ThisPackages Using ThisMost Recent CommitTotal ReleasesLatest ReleaseOpen IssuesLicenseLanguage
Platformio Vscode Ide1,104223 months ago25February 04, 2022175apache-2.0JavaScript
PlatformIO IDE for VSCode: The next generation integrated development environment for IoT
Hadbadge2019_fpgasoc154
4 months ago18otherC
FPGA SoC code and application example for Hackaday Supercon 2019 badge
Koheron Sdk91
3 months ago35July 20, 202345otherTcl
SDK for FPGA / Linux Instruments
Multizone Sdk74
2 months agootherC
MultiZone® Security TEE is the quick and safe way to add security and separation to any RISC-V processors. The RISC-V standard ISA doesn't define TrustZone-like primitives to provide hardware separation. To shield critical functionality from untrusted third-party components, MultiZone provides hardware-enforced, software-defined separation of multi
Scr1 Sdk65
6 months agootherC
open-source SDKs for the SCR1 core
Nuclei Linux Sdk32
3 months ago13apache-2.0Makefile
Nuclei RISC-V Linux Software Development Kit
Celex4 Opalkelly13
4 years ago6apache-2.0C++
SDK for CeleX4 sensor.
Xilinx Deep Learning Nexys411
5 years agoVHDL
Implemented Darius IP (originally target PYNQ) of convolution and maxpool on Xilinx FPGA with SDK
Bce Fpga Dev Kit9
6 years agootherVHDL
bce-fpga-dev-kit
Alternatives To Xilinx Deep Learning Nexys4
Select To Compare


Alternative Project Comparisons
Popular Sdk Projects
Popular Fpga Projects
Popular Libraries Categories
Related Searches

Get A Weekly Email With Trending Projects For These Categories
No Spam. Unsubscribe easily at any time.
Machine Learning
Sdk
Fpga
Convolution
Vhdl
Tcl