Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
---|---|---|---|---|---|---|---|---|---|---|
Scamp Cpu | 279 | 5 months ago | unlicense | Slash | ||||||
A homebrew 16-bit CPU with a homebrew Unix-like-ish operating system. | ||||||||||
Eurorack Pmod | 137 | 4 months ago | 5 | other | SystemVerilog | |||||
Hardware and gateware for getting started in FPGA-based audio synthesis with open source tools. | ||||||||||
Icemu | 113 | 6 years ago | 5 | October 31, 2017 | 1 | lgpl-3.0 | C | |||
Emulate Integrated Circuits at the logic level | ||||||||||
Sol 1 | 57 | 4 months ago | 1 | C | ||||||
Sol-1: A CPU/Computer System made from 74 series logic. | ||||||||||
Virtualtap | 52 | 7 months ago | 4 | gpl-2.0 | Verilog | |||||
Mod kit for the Virtual Boy to make it output VGA or RGB video | ||||||||||
Getting Started | 46 | 4 years ago | 25 | Shell | ||||||
List of ideas for getting started with TimVideos projects | ||||||||||
Max1000 Tutorial | 30 | 4 years ago | Verilog | |||||||
Tutorial and example projects for the Arrow MAX1000 FPGA board | ||||||||||
Neochips | 23 | a year ago | gpl-2.0 | Verilog | ||||||
Replacement "chips" for NeoGeo systems | ||||||||||
Discretize | 10 | 4 months ago | bsd-3-clause | C++ | ||||||
A Yosys pass and technology library + scripts for implementing a HDL design in discretie FETs for layout in KiCad | ||||||||||
Digital_lab | 8 | 4 years ago | mit | Verilog | ||||||
Laboratory works for digital electronics course in Kyiv Polytechnic Institute, Department of Design of Electronic Digital Equipment, Electronics faculty |