Switched Multiported Ram
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Vtr Verilog To Routing | 925 | 5 months ago | 447 | other | C++ | |||||
| Verilog to Routing -- Open Source CAD Flow for FPGA Research | ||||||||||
| Opentimer | 368 | 2 years ago | 48 | other | Verilog | |||||
| A High-performance Timing Analysis Tool for VLSI Systems | ||||||||||
| Spydrnet | 66 | 8 months ago | 21 | September 14, 2023 | 44 | bsd-3-clause | Python | |||
| A flexible framework for analyzing and transforming FPGA netlists. Official repository. | ||||||||||
| Rdf 2019 | 14 | 4 years ago | mit | Verilog | ||||||
| DATC RDF | ||||||||||
| Study Materials | 12 | a year ago | mit | |||||||
| Nem Relay Cad | 12 | 2 years ago | mit | HTML | ||||||
| Parametric NEM relay design with layout generation (KLayout: GDSII, DXF), FEM (Ansys/COMSOL), SPICE models, Liberty models, and more | ||||||||||
| Switched Multiported Ram | 6 | 9 years ago | other | Verilog | ||||||
| Switched SRAM-based Multi-ported RAM | ||||||||||
| Bsg_pipeclean_suite | 6 | 4 years ago | bsd-3-clause | Verilog | ||||||
| Libcircuit | 6 | 6 years ago | other | Verilog | ||||||
| libCircuit is a C++ Library for EDA software development | ||||||||||
| Fmcw | 5 | 4 years ago | 5 | apache-2.0 | Python | |||||
| 6GHz frequency-modulated continuous-wave radar with real-time range detection | ||||||||||
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