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5 search results found

Ipxact2systemverilog ⭐ 55

Translates IPXACT XML to synthesizable VHDL or SystemVerilog

Verilog Utils ⭐ 32

native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches

Sdaccel_chisel_integration ⭐ 16

Chisel Project for Integrating RTL code into SDAccel

Hdlgen Chatgpt ⭐ 9

HDLGen-ChatGPT, works in tandem with ChatGPT-3.5 chat interface to enable fast digital systems design and test specification capture, and automatic generation of both VHDL and Verilog models, and testbenches, and AMD Vivado and Intel Quartus Electronic Design Automation (EDA) project

F4pga V2x ⭐ 8

Tool for converting specialized annotated Verilog models into XML needed for Verilog to Routing flow.

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