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Riscv V Spec ⭐ 801

Working draft of the proposed RISC-V V vector extension

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

Imperas Riscv Tests ⭐ 123

Simd_utils ⭐ 65

A header only library implementing common mathematical functions using SIMD intrinsics

Riscv Vectorized Benchmark Suite ⭐ 48

RiVEC Bencmark Suite

Dl_accelerator ⭐ 44

Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions

Rvv Kernels ⭐ 16

Implements kernels with RISC-V Vector

Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension

Risc V Cpu ⭐ 6

A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.

RISC-V vector and other assembly code examples

Rvv Encoder ⭐ 5

RISC-V V Extension Encoder

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