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Search results for port verilog

15 search results found

Ao486_mister ⭐ 223

ao486 port for MiSTer

A very primitive but hopefully self-educational CPU in Verilog

Upduino v2 with the ice40 up5k FPGA demos

A collection of debugging busses developed and presented at zipcpu.com

Atari ST/STe core for FPGAs

Vim Verilog Instance ⭐ 22

verilog_instance.vim: create instantiation of ports from port declaration

Hardcaml_of_verilog ⭐ 15

Convert Verilog to a Hardcaml design

Systemc Tutorial ⭐ 11

Brief SystemC getting started tutorial

Panog2_nes ⭐ 8

Port of Brian Bennet's NES Emulator for the second generation Panologic thin client

Hardcaml Yosys ⭐ 8

[DEPRECATED] Import verilog designs into hardcaml using yosys

Autofpga Demo ⭐ 6

A demonstration of how AutoFPGA can compose a design from simple components

Verilogpp ⭐ 5

Rautanoppa ⭐ 5

Hardware random number generator for FPGAs

Ulx3s Blinky ⭐ 5

A blinky project for the ULX3S v3.0.3 FPGA board

Eda Tools ⭐ 5

Verilog Gate-Level Studio

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