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10 search results found
Openlane
⭐
1,148
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Poc
⭐
324
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
Openlane2
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99
The next generation of OpenLane, rewritten from scratch with a modular architecture
Padring
⭐
19
A padring generator for ASICs
Ogre
⭐
19
Global Router Built for ICCAD Contest 2019
Ml2tikz
⭐
16
maskLayout to tikzpicture converter for Cadence Virtuoso
Magic_vlsi_examples
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16
Some simple examples for the Magic VLSI physical chip layout tool.
Gatery
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14
Gatery, a library for circuit design.
Mastering Fpgasic Book
⭐
8
📖 Mastering FPGASIC Book
Sch2tikz
⭐
8
schematic to tikzpicture converter for Cadence Virtuoso
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