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The Top 23 Scala Risc V Open Source Projects

Open source projects categorized as Scala Risc V
Xiangshan ⭐ 4,180
Open-source high-performance RISC-V processor
most recent commit 3 months ago
Rocket Chip ⭐ 2,988
Rocket Chip Generator
total releases 9most recent commit 23 days ago
Riscv Boom ⭐ 1,524
SonicBOOM: The Berkeley Out-of-Order Machine
most recent commit 3 months ago
Firesim ⭐ 778
FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
most recent commit 3 months ago
Riscv Mini ⭐ 427
Simple RISC-V 3-stage Pipeline in Chisel
most recent commit 7 months ago
Dana ⭐ 147
Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
most recent commit 4 years ago
Saxonsoc ⭐ 133
SoC based on VexRiscv and ICE40 UP5K
most recent commit 4 months ago
Awesome Riscv ⭐ 96
😎 A curated list of awesome RISC-V implementations
most recent commit a year ago
Chiselv ⭐ 88
A RISC-V Core (RV32I) written in Chisel HDL
most recent commit 4 months ago
Yatcpu ⭐ 61
Yet another toy CPU.
most recent commit 6 months ago
Riscv Sodor ⭐ 56
educational microarchitectures for risc-v isa
most recent commit 5 years ago
Dl_accelerator ⭐ 44
Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions
most recent commit 4 years ago
Riscv Fivestage ⭐ 41
Marginally better than redstone
most recent commit 4 years ago
Fuxi ⭐ 40
Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
most recent commit 3 years ago
Tree Core Cpu ⭐ 29
A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.
most recent commit 6 months ago
Proteus ⭐ 27
The SpinalHDL design of the Proteus core, an extensible RISC-V core.
most recent commit 7 months ago
Learn Rv32i Asap ⭐ 25
A Simple As Possible RISCV-32I core with debug module.
most recent commit 4 years ago
Chiffre ⭐ 25
A fault-injection framework using Chisel and FIRRTL
most recent commit a year ago
Kyogenrv ⭐ 25
The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
most recent commit 3 years ago
Boom Template ⭐ 23
A template for building new projects/platforms using the BOOM core.
most recent commit 5 years ago
Rift2core ⭐ 21
Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
total releases 5most recent commit a year ago
Systemoncat ⭐ 17
An SoC with multiple RISC-V IMA processors.
most recent commit 6 years ago
Quasar ⭐ 13
Quasar 2.0: Chisel equivalent of SweRV-EL2
most recent commit 3 years ago
The 2 Latest Releases In Scala Risc V Open Source Projects
Rocket Chip ⭐ 2,988
Rocket Chip Generator
total releases 9latest release May 14, 2020most recent commit 23 days ago
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