Riscv Fivestage
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Scr1 | 688 | 7 months ago | 3 | other | SystemVerilog | |||||
| SCR1 is a high-quality open-source RISC-V MCU core in Verilog | ||||||||||
| Riscv Mini | 427 | 7 months ago | 3 | other | Scala | |||||
| Simple RISC-V 3-stage Pipeline in Chisel | ||||||||||
| Force Riscv | 183 | 6 months ago | 12 | other | C++ | |||||
| Instruction Set Generator initially contributed by Futurewei | ||||||||||
| Riscv Bitmanip | 174 | a year ago | 44 | cc-by-4.0 | Makefile | |||||
| Working draft of the proposed RISC-V Bitmanipulation extension | ||||||||||
| Imperas Riscv Tests | 123 | 6 months ago | 12 | C | ||||||
| Cmake Tutorial | 59 | 3 months ago | mit | Shell | ||||||
| A short tutorial on how to build and test embedded software using the IAR C/C++ Compiler alongside CMake | ||||||||||
| Rocket Rocc Examples | 43 | 4 years ago | 3 | other | C | |||||
| Tests for example Rocket Custom Coprocessors | ||||||||||
| Riscv Fivestage | 41 | 4 years ago | 1 | apache-2.0 | Scala | |||||
| Marginally better than redstone | ||||||||||
| Fuxi | 40 | 3 years ago | gpl-3.0 | Verilog | ||||||
| Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3. | ||||||||||
| Gateware | 26 | 5 months ago | 2 | other | Verilog | |||||
| IP submodules, formatted for easier CI integration | ||||||||||
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