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The Top 16 Fpga Verilog Hdl Open Source Projects

Open source projects categorized as Fpga Verilog Hdl
Categories > Hardware > Fpga
Categories > Verilog Hdl
Vunit ⭐ 678
VUnit is a unit testing framework for VHDL/SystemVerilog
dependent packages 5total releases 87most recent commit 25 days agopypi vunit-hdl} Downloads
Cores ⭐ 302
Various HDL (Verilog) IP Cores
most recent commit 3 years ago
Async_fifo ⭐ 173
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
most recent commit a year ago
Image Processing ⭐ 123
Image Processing Toolbox in Verilog using Basys3 FPGA
most recent commit 7 months ago
Fakepga ⭐ 66
Simulating Verilog designs on a microcontroller
most recent commit a year ago
Higan Verilog ⭐ 33
This is a higan/Verilator co-simulation example/framework
most recent commit 6 years ago
Riscv_cpu ⭐ 30
A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL
most recent commit 4 years ago
Uart ⭐ 25
A simple implementation of a UART modem in Verilog.
most recent commit 2 years ago
Deep Darkfantasy ⭐ 15
Global Dark Mode for ALL apps on ANY platforms.
most recent commit 3 years ago
100daysofrtl ⭐ 12
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
most recent commit 10 months ago
Hdl Deflate ⭐ 12
FPGA implementation of deflate (de)compress RFC 1950/1951
most recent commit 5 years ago
Fpga_spi ⭐ 11
Connecting FPGA and Arduino using SPI.
most recent commit 2 years ago
Fpga Bicubic Interpolation ⭐ 10
use Verilog HDL implemente bicubic interpolation in FPGA
most recent commit 4 years ago
Quickspi ⭐ 9
Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
most recent commit 6 years ago
Openxc7 Tetrisaraj ⭐ 7
Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented with SW in the bare-metal 'C' they, together, make for this classic game. Except that it's now, in the standard BiH tradition, with a twist of our own.
most recent commit 4 months ago
Viterbi Decoder In Verilog ⭐ 6
An efficient implementation of the Viterbi decoding algorithm in Verilog
most recent commit 6 years ago
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