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The Top 19 Cpu Rtl Open Source Projects

Open source projects categorized as Cpu Rtl
Darkriscv ⭐ 1,795
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
most recent commit 5 months ago
Riscv_vhdl ⭐ 552
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
most recent commit 4 months ago
Concurrency ⭐ 537
Java 并发编程知识梳理以及常见处理模式 features and patterns
most recent commit 2 years ago
Nontrivial Mips ⭐ 362
NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
most recent commit 4 years ago
Ustc Rvsoc ⭐ 261
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。
most recent commit 7 months ago
Tekno Kizil ⭐ 129
KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi
most recent commit 9 months ago
Toooba ⭐ 126
RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
most recent commit 9 months ago
Oldland Cpu ⭐ 89
Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools
most recent commit 8 years ago
Realtek Mips Sdks ⭐ 50
Realtek Network SoC/CPU toolchains (including support for Lexra based chips)
most recent commit a year ago
Simplecpu ⭐ 30
An open source CPU design and verification platform for academia
most recent commit 4 years ago
Tree Core Cpu ⭐ 29
A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.
most recent commit 6 months ago
Proteus ⭐ 27
The SpinalHDL design of the Proteus core, an extensible RISC-V core.
most recent commit 7 months ago
Spinaldev ⭐ 12
Docker Development Environment for SpinalHDL
most recent commit 4 years ago
Udarkrisc ⭐ 9
u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV
most recent commit 9 months ago
Cpu ⭐ 9
MIPS CPU
most recent commit 3 years ago
Pequeno_riscv ⭐ 8
Pequeno aka pqr5 is a pipelined in-order RISC-V CPU Core compliant with RV32I
most recent commit 4 months ago
Risc63 ⭐ 8
Custom 64-bit pipelined RISC processor
most recent commit a year ago
2stage ⭐ 7
a simple 2 stage cpu in verilog
most recent commit 3 years ago
J68_cpu ⭐ 6
Small microcoded 68000 verilog softcore
most recent commit 5 years ago
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